RISC-V: Add support for XCVsimd extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* NEWS: Updated.
* config/tc-riscv.c (validate_riscv_insn): Add custom operands.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Note XCVsimd as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/march-help.l: Add xcvsimd.
* testsuite/gas/riscv/x-cv-simd.d: New test.
* testsuite/gas/riscv/x-cv-simd.s: New test.
* testsuite/gas/riscv/x-cv-simd-fail.d: New test.
* testsuite/gas/riscv/x-cv-simd-fail.l: New test.
* testsuite/gas/riscv/x-cv-simd-fail.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK macros
for XCVsimd.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVsimd.
(enum riscv_insn_class): Add the XCVsimd instruction class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add custom operands.
* riscv-opc.c: Add XCVsimd instructions.
14 files changed
