)]}'
{
  "commit": "a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0",
  "tree": "b62a75e4faa6bd99b6af833302c239d1457d2e74",
  "parents": [
    "92d8946670571118cccdbcd36d35300af33da4af"
  ],
  "author": {
    "name": "Victor Do Nascimento",
    "email": "victor.donascimento@arm.com",
    "time": "Wed Nov 15 17:21:39 2023 +0000"
  },
  "committer": {
    "name": "Victor Do Nascimento",
    "email": "victor.donascimento@arm.com",
    "time": "Tue Jan 09 10:16:40 2024 +0000"
  },
  "message": "aarch64: Implement TLBIP 128-bit instruction\n\nThe addition of 128-bit page table descriptors and, with it, the\naddition of 128-bit system registers for these means that special\n\"invalidate translation table entry\" instructions are needed to cope\nwith the new 128-bit model.  This is introduced with the `tlbpi\u0027\ninstruction, implemented here.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "539bfa27e0e5d52f7b9140989e47c44c1706c78c",
      "old_mode": 33188,
      "old_path": "gas/config/tc-aarch64.c",
      "new_id": "6a8ebe4d64828c6bd657a61ab688357915171de4",
      "new_mode": 33188,
      "new_path": "gas/config/tc-aarch64.c"
    },
    {
      "type": "modify",
      "old_id": "b81475fc70310bf31d0633f6ecbea5a163034108",
      "old_mode": 33188,
      "old_path": "include/opcode/aarch64.h",
      "new_id": "768caecde1d14b4805271e814e88352186ac412f",
      "new_mode": 33188,
      "new_path": "include/opcode/aarch64.h"
    },
    {
      "type": "modify",
      "old_id": "ec14e4b97d670e17d27fbd033acd4060d1e8b82f",
      "old_mode": 33188,
      "old_path": "opcodes/aarch64-tbl.h",
      "new_id": "bb8f343ffa611253e568f9a9899e2c170ce7a6dd",
      "new_mode": 33188,
      "new_path": "opcodes/aarch64-tbl.h"
    }
  ]
}