blob: dc99dae9c42e158ea62f3dbd07cb137e4dce689c [file] [log] [blame]
# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI
# mach: xscale
# as: -mcpu=xscale+iwmmxt
.include "testutils.inc"
start
.global waligni
waligni:
# Enable access to CoProcessors 0 & 1 before
# we attempt these instructions.
mvi_h_gr r1, 3
mcr p15, 0, r1, cr15, cr1, 0
# Test 2 byte align
mvi_h_gr r0, 0x12345678
mvi_h_gr r1, 0x9abcdef0
mvi_h_gr r2, 0x11111111
mvi_h_gr r3, 0x00000000
mvi_h_gr r4, 0
mvi_h_gr r5, 0
tmcrr wr0, r0, r1
tmcrr wr1, r2, r3
tmcrr wr2, r4, r5
waligni wr2, wr0, wr1, #2
tmrrc r0, r1, wr0
tmrrc r2, r3, wr1
tmrrc r4, r5, wr2
test_h_gr r0, 0x12345678
test_h_gr r1, 0x9abcdef0
test_h_gr r2, 0x11111111
test_h_gr r3, 0x00000000
test_h_gr r4, 0xdef01234
test_h_gr r5, 0x11119abc
pass