| # Intel(r) Wireless MMX(tm) technology testcase for WSUB |
| # mach: xscale |
| # as: -mcpu=xscale+iwmmxt |
| |
| .include "testutils.inc" |
| |
| start |
| |
| .global wsub |
| wsub: |
| # Enable access to CoProcessors 0 & 1 before |
| # we attempt these instructions. |
| |
| mvi_h_gr r1, 3 |
| mcr p15, 0, r1, cr15, cr1, 0 |
| |
| # Test Unsaturated Byte subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubb wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abcdef |
| |
| # Test Unsigned saturated Byte subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubbus wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abcd00 |
| |
| # Test Signed saturated Byte subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubbss wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abcdef |
| |
| # Test Unsaturated Halfword subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubh wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abccef |
| |
| # Test Unsigned saturated Halfword subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubhus wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abccef |
| |
| # Test Signed saturated Halfword subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubhss wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abccef |
| |
| # Test Unsaturated Word subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubw wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abccef |
| |
| # Test Unsigned saturated Word subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubwus wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abccef |
| |
| # Test Signed saturated Word subtraction |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| wsubwss wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x01234567 |
| test_h_gr r5, 0x89abccef |
| |
| pass |
