| //Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp | |
| // Spec Reference: alu2op shadd 2 | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| imm32 r0, 0x03417990; | |
| imm32 r1, 0x12315678; | |
| imm32 r2, 0x23416789; | |
| imm32 r3, 0x3451789a; | |
| imm32 r4, 0x856189ab; | |
| imm32 r5, 0x96719abc; | |
| imm32 r6, 0xa781abcd; | |
| imm32 r7, 0xb891bcde; | |
| R1 = ( R1 + R0 ) << 2; | |
| R2 = ( R2 + R0 ) << 2; | |
| R3 = ( R3 + R0 ) << 2; | |
| R4 = ( R4 + R0 ) << 2; | |
| R5 = ( R5 + R0 ) << 2; | |
| R6 = ( R6 + R0 ) << 2; | |
| R7 = ( R7 + R0 ) << 2; | |
| R0 = ( R0 + R0 ) << 2; | |
| CHECKREG r0, 0x1A0BCC80; | |
| CHECKREG r1, 0x55CB4020; | |
| CHECKREG r2, 0x9A0B8464; | |
| CHECKREG r3, 0xDE4BC8A8; | |
| CHECKREG r4, 0x228C0CEC; | |
| CHECKREG r5, 0x66CC5130; | |
| CHECKREG r6, 0xAB0C9574; | |
| CHECKREG r7, 0xEF4CD9B8; | |
| imm32 r0, 0x03457290; | |
| imm32 r1, 0x12345278; | |
| imm32 r2, 0x23456289; | |
| imm32 r3, 0x3456729a; | |
| imm32 r4, 0x856782ab; | |
| imm32 r5, 0x967892bc; | |
| imm32 r6, 0xa789a2cd; | |
| imm32 r7, 0xb89ab2de; | |
| R0 = ( R0 + R1 ) << 2; | |
| R2 = ( R2 + R1 ) << 2; | |
| R3 = ( R3 + R1 ) << 2; | |
| R4 = ( R4 + R1 ) << 2; | |
| R5 = ( R5 + R1 ) << 2; | |
| R6 = ( R6 + R1 ) << 2; | |
| R7 = ( R7 + R1 ) << 2; | |
| R1 = ( R1 + R1 ) << 2; | |
| CHECKREG r0, 0x55E71420; | |
| CHECKREG r1, 0x91A293C0; | |
| CHECKREG r2, 0xD5E6D404; | |
| CHECKREG r3, 0x1A2B1448; | |
| CHECKREG r4, 0x5E6F548C; | |
| CHECKREG r5, 0xA2B394D0; | |
| CHECKREG r6, 0xE6F7D514; | |
| CHECKREG r7, 0x2B3C1558; | |
| imm32 r0, 0x03457930; | |
| imm32 r1, 0x12345638; | |
| imm32 r2, 0x23456739; | |
| imm32 r3, 0x3456783a; | |
| imm32 r4, 0x8567893b; | |
| imm32 r5, 0x96789a3c; | |
| imm32 r6, 0xa789ab3d; | |
| imm32 r7, 0xb89abc3e; | |
| R0 = ( R0 + R2 ) << 2; | |
| R1 = ( R1 + R2 ) << 2; | |
| R3 = ( R3 + R2 ) << 2; | |
| R4 = ( R4 + R2 ) << 2; | |
| R5 = ( R5 + R2 ) << 2; | |
| R6 = ( R6 + R2 ) << 2; | |
| R7 = ( R7 + R2 ) << 2; | |
| R2 = ( R2 + R2 ) << 2; | |
| CHECKREG r0, 0x9A2B81A4; | |
| CHECKREG r1, 0xD5E6F5C4; | |
| CHECKREG r2, 0x1A2B39C8; | |
| CHECKREG r3, 0x5E6F7DCC; | |
| CHECKREG r4, 0xA2B3C1D0; | |
| CHECKREG r5, 0xE6F805D4; | |
| CHECKREG r6, 0x2B3C49D8; | |
| CHECKREG r7, 0x6F808DDC; | |
| imm32 r0, 0x04457990; | |
| imm32 r1, 0x14345678; | |
| imm32 r2, 0x24456789; | |
| imm32 r3, 0x3456789a; | |
| imm32 r4, 0x846789ab; | |
| imm32 r5, 0x94789abc; | |
| imm32 r6, 0xa489abcd; | |
| imm32 r7, 0xb49abcde; | |
| R0 = ( R0 + R3 ) << 2; | |
| R1 = ( R1 + R3 ) << 2; | |
| R2 = ( R2 + R3 ) << 2; | |
| R4 = ( R4 + R3 ) << 2; | |
| R5 = ( R5 + R3 ) << 2; | |
| R6 = ( R6 + R3 ) << 2; | |
| R7 = ( R7 + R3 ) << 2; | |
| R3 = ( R3 + R3 ) << 2; | |
| CHECKREG r0, 0xE26FC8A8; | |
| CHECKREG r1, 0x222B3C48; | |
| CHECKREG r2, 0x626F808C; | |
| CHECKREG r3, 0xA2B3C4D0; | |
| CHECKREG r4, 0xE2F80914; | |
| CHECKREG r5, 0x233C4D58; | |
| CHECKREG r6, 0x6380919C; | |
| CHECKREG r7, 0xA3C4D5E0; | |
| imm32 r0, 0x03417990; | |
| imm32 r1, 0x12315678; | |
| imm32 r2, 0x23416789; | |
| imm32 r3, 0x3451789a; | |
| imm32 r4, 0x856189ab; | |
| imm32 r5, 0x96719abc; | |
| imm32 r6, 0xa781abcd; | |
| imm32 r7, 0xb891bcde; | |
| R0 = ( R0 + R4 ) << 2; | |
| R1 = ( R1 + R4 ) << 2; | |
| R2 = ( R2 + R4 ) << 2; | |
| R3 = ( R3 + R4 ) << 2; | |
| R5 = ( R5 + R4 ) << 2; | |
| R6 = ( R6 + R4 ) << 2; | |
| R7 = ( R7 + R4 ) << 2; | |
| R4 = ( R4 + R4 ) << 2; | |
| CHECKREG r0, 0x228C0CEC; | |
| CHECKREG r1, 0x5E4B808C; | |
| CHECKREG r2, 0xA28BC4D0; | |
| CHECKREG r3, 0xE6CC0914; | |
| CHECKREG r4, 0x2B0C4D58; | |
| CHECKREG r5, 0x6F4C919C; | |
| CHECKREG r6, 0xB38CD5E0; | |
| CHECKREG r7, 0xF7CD1A24; | |
| imm32 r0, 0x03457290; | |
| imm32 r1, 0x12345278; | |
| imm32 r2, 0x23456289; | |
| imm32 r3, 0x3456729a; | |
| imm32 r4, 0x856782ab; | |
| imm32 r5, 0x967892bc; | |
| imm32 r6, 0xa789a2cd; | |
| imm32 r7, 0xb89ab2de; | |
| R0 = ( R0 + R5 ) << 2; | |
| R1 = ( R1 + R5 ) << 2; | |
| R2 = ( R2 + R5 ) << 2; | |
| R3 = ( R3 + R5 ) << 2; | |
| R4 = ( R4 + R5 ) << 2; | |
| R6 = ( R6 + R5 ) << 2; | |
| R7 = ( R7 + R5 ) << 2; | |
| R5 = ( R5 + R5 ) << 2; | |
| CHECKREG r0, 0x66F81530; | |
| CHECKREG r1, 0xA2B394D0; | |
| CHECKREG r2, 0xE6F7D514; | |
| CHECKREG r3, 0x2B3C1558; | |
| CHECKREG r4, 0x6F80559C; | |
| CHECKREG r5, 0xB3C495E0; | |
| CHECKREG r6, 0xF808D624; | |
| CHECKREG r7, 0x3C4D1668; | |
| imm32 r0, 0x03457930; | |
| imm32 r1, 0x12345638; | |
| imm32 r2, 0x23456739; | |
| imm32 r3, 0x3456783a; | |
| imm32 r4, 0x8567893b; | |
| imm32 r5, 0x96789a3c; | |
| imm32 r6, 0xa789ab3d; | |
| imm32 r7, 0xb89abc3e; | |
| R0 = ( R0 + R6 ) << 2; | |
| R1 = ( R1 + R6 ) << 2; | |
| R2 = ( R2 + R6 ) << 2; | |
| R3 = ( R3 + R6 ) << 2; | |
| R4 = ( R4 + R6 ) << 2; | |
| R5 = ( R5 + R6 ) << 2; | |
| R7 = ( R7 + R6 ) << 2; | |
| R6 = ( R6 + R6 ) << 2; | |
| CHECKREG r0, 0xAB3C91B4; | |
| CHECKREG r1, 0xE6F805D4; | |
| CHECKREG r2, 0x2B3C49D8; | |
| CHECKREG r3, 0x6F808DDC; | |
| CHECKREG r4, 0xB3C4D1E0; | |
| CHECKREG r5, 0xF80915E4; | |
| CHECKREG r6, 0x3C4D59E8; | |
| CHECKREG r7, 0x80919DEC; | |
| imm32 r0, 0x04457990; | |
| imm32 r1, 0x14345678; | |
| imm32 r2, 0x24456789; | |
| imm32 r3, 0x3456789a; | |
| imm32 r4, 0x846789ab; | |
| imm32 r5, 0x94789abc; | |
| imm32 r6, 0xa489abcd; | |
| imm32 r7, 0xb49abcde; | |
| R0 = ( R0 + R7 ) << 2; | |
| R1 = ( R1 + R7 ) << 2; | |
| R2 = ( R2 + R7 ) << 2; | |
| R3 = ( R3 + R7 ) << 2; | |
| R4 = ( R4 + R7 ) << 2; | |
| R5 = ( R5 + R7 ) << 2; | |
| R6 = ( R6 + R7 ) << 2; | |
| R7 = ( R7 + R7 ) << 2; | |
| CHECKREG r0, 0xE380D9B8; | |
| CHECKREG r1, 0x233C4D58; | |
| CHECKREG r2, 0x6380919C; | |
| CHECKREG r3, 0xA3C4D5E0; | |
| CHECKREG r4, 0xE4091A24; | |
| CHECKREG r5, 0x244D5E68; | |
| CHECKREG r6, 0x6491A2AC; | |
| CHECKREG r7, 0xA4D5E6F0; | |
| pass |