sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s

//Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp
// Spec Reference: compi2opd dregs += imm7 negative
# mach: bfin

.include "testutils.inc"
	start


INIT_R_REGS 0;

R0 += 0;
R1 += -1;
R2 += -2;
R3 += -3;
R4 += -4;
R5 += -5;
R6 += -6;
R7 += -7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFE;
CHECKREG r3, 0xFFFFFFFD;
CHECKREG r4, 0xFFFFFFFC;
CHECKREG r5, 0xFFFFFFFB;
CHECKREG r6, 0xFFFFFFFA;
CHECKREG r7, 0xFFFFFFF9;

R0 += -8;
R1 += -9;
R2 += -10;
R3 += -11;
R4 += -12;
R5 += -13;
R6 += -14;
R7 += -15;
CHECKREG r0, 0xFFFFFFF8;
CHECKREG r1, 0xFFFFFFF6;
CHECKREG r2, 0xFFFFFFF4;
CHECKREG r3, 0xFFFFFFF2;
CHECKREG r4, 0xFFFFFFF0;
CHECKREG r5, 0xFFFFFFEE;
CHECKREG r6, 0xFFFFFFEC;
CHECKREG r7, 0xFFFFFFEA;

R0 += -16;
R1 += -17;
R2 += -18;
R3 += -19;
R4 += -20;
R5 += -21;
R6 += -22;
R7 += -23;
CHECKREG r0, 0xFFFFFFE8;
CHECKREG r1, 0xFFFFFFE5;
CHECKREG r2, 0xFFFFFFE2;
CHECKREG r3, 0xFFFFFFDF;
CHECKREG r4, 0xFFFFFFDC;
CHECKREG r5, 0xFFFFFFD9;
CHECKREG r6, 0xFFFFFFD6;
CHECKREG r7, 0xFFFFFFD3;

R0 += -24;
R1 += -25;
R2 += -26;
R3 += -27;
R4 += -28;
R5 += -29;
R6 += -30;
R7 += -31;
CHECKREG r0, 0xFFFFFFD0;
CHECKREG r1, 0xFFFFFFCC;
CHECKREG r2, 0xFFFFFFC8;
CHECKREG r3, 0xFFFFFFC4;
CHECKREG r4, 0xFFFFFFC0;
CHECKREG r5, 0xFFFFFFBC;
CHECKREG r6, 0xFFFFFFB8;
CHECKREG r7, 0xFFFFFFB4;

R0 += -32;
R1 += -33;
R2 += -34;
R3 += -35;
R4 += -36;
R5 += -37;
R6 += -38;
R7 += -39;
CHECKREG r0, 0xFFFFFFB0;
CHECKREG r1, 0xFFFFFFAB;
CHECKREG r2, 0xFFFFFFA6;
CHECKREG r3, 0xFFFFFFA1;
CHECKREG r4, 0xFFFFFF9C;
CHECKREG r5, 0xFFFFFF97;
CHECKREG r6, 0xFFFFFF92;
CHECKREG r7, 0xFFFFFF8D;

R0 += -40;
R1 += -41;
R2 += -42;
R3 += -43;
R4 += -44;
R5 += -45;
R6 += -46;
R7 += -47;
CHECKREG r0, 0xFFFFFF88;
CHECKREG r1, 0xFFFFFF82;
CHECKREG r2, 0xFFFFFF7C;
CHECKREG r3, 0xFFFFFF76;
CHECKREG r4, 0xFFFFFF70;
CHECKREG r5, 0xFFFFFF6A;
CHECKREG r6, 0xFFFFFF64;
CHECKREG r7, 0xFFFFFF5E;

R0 += -48;
R1 += -49;
R2 += -50;
R3 += -51;
R4 += -52;
R5 += -53;
R6 += -54;
R7 += -55;
CHECKREG r0, 0xFFFFFF58;
CHECKREG r1, 0xFFFFFF51;
CHECKREG r2, 0xFFFFFF4A;
CHECKREG r3, 0xFFFFFF43;
CHECKREG r4, 0xFFFFFF3C;
CHECKREG r5, 0xFFFFFF35;
CHECKREG r6, 0xFFFFFF2E;
CHECKREG r7, 0xFFFFFF27;

R0 += -56;
R1 += -57;
R2 += -58;
R3 += -59;
R4 += -60;
R5 += -61;
R6 += -62;
R7 += -63;
CHECKREG r0, 0xFFFFFF20;
CHECKREG r1, 0xFFFFFF18;
CHECKREG r2, 0xFFFFFF10;
CHECKREG r3, 0xFFFFFF08;
CHECKREG r4, 0xFFFFFF00;
CHECKREG r5, 0xFFFFFEF8;
CHECKREG r6, 0xFFFFFEF0;
CHECKREG r7, 0xFFFFFEE8;

R0 += -64;
R1 += -64;
R2 += -64;
R3 += -64;
R4 += -64;
R5 += -64;
R6 += -64;
R7 += -64;
CHECKREG r0, 0xFFFFFEE0;
CHECKREG r1, 0xFFFFFED8;
CHECKREG r2, 0xFFFFFED0;
CHECKREG r3, 0xFFFFFEC8;
CHECKREG r4, 0xFFFFFEC0;
CHECKREG r5, 0xFFFFFEB8;
CHECKREG r6, 0xFFFFFEB0;
CHECKREG r7, 0xFFFFFEA8;

pass