| //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_p/c_dsp32alu_rl_rnd12_p.dsp | |
| // Spec Reference: dsp32alu dreg (half) | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| R0 = 0; | |
| ASTAT = R0; | |
| imm32 r0, 0x85678011; | |
| imm32 r1, 0x9189a11d; | |
| imm32 r2, 0xa4245235; | |
| imm32 r3, 0xb6637747; | |
| imm32 r4, 0xc67849db; | |
| imm32 r5, 0x6789a5fd; | |
| imm32 r6, 0xe4445565; | |
| imm32 r7, 0x86667707; | |
| R0.L = R0 + R0 (RND12); | |
| R1.L = R0 + R1 (RND12); | |
| R2.L = R0 + R2 (RND12); | |
| R3.L = R0 + R3 (RND12); | |
| R4.L = R0 + R4 (RND12); | |
| R5.L = R0 + R5 (RND12); | |
| R6.L = R0 + R6 (RND12); | |
| R7.L = R0 + R7 (RND12); | |
| CHECKREG r0, 0x85678000; | |
| CHECKREG r1, 0x91898000; | |
| CHECKREG r2, 0xA4248000; | |
| CHECKREG r3, 0xB6638000; | |
| CHECKREG r4, 0xC6788000; | |
| CHECKREG r5, 0x67898000; | |
| CHECKREG r6, 0xE4448000; | |
| CHECKREG r7, 0x86668000; | |
| imm32 r0, 0x75678921; | |
| imm32 r1, 0x2789ab14; | |
| imm32 r2, 0xd4745515; | |
| imm32 r3, 0x4d677767; | |
| imm32 r4, 0x56d8791b; | |
| imm32 r5, 0x678dab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86a6d777; | |
| R0.L = R1 + R0 (RND12); | |
| R1.L = R1 + R1 (RND12); | |
| R2.L = R1 + R2 (RND12); | |
| R3.L = R1 + R3 (RND12); | |
| R4.L = R1 + R4 (RND12); | |
| R5.L = R1 + R5 (RND12); | |
| R6.L = R1 + R6 (RND12); | |
| R7.L = R1 + R7 (RND12); | |
| CHECKREG r0, 0x75677FFF; | |
| CHECKREG r1, 0x27897FFF; | |
| CHECKREG r2, 0xD474bfdd; | |
| CHECKREG r3, 0x4D677fff; | |
| CHECKREG r4, 0x56D87FFF; | |
| CHECKREG r5, 0x678D7FFF; | |
| CHECKREG r6, 0x74447FFF; | |
| CHECKREG r7, 0x86A68000; | |
| imm32 r0, 0x55678911; | |
| imm32 r1, 0x2689ab2d; | |
| imm32 r2, 0x3d44551a; | |
| imm32 r3, 0x469677cd; | |
| imm32 r4, 0xa67a89bb; | |
| imm32 r5, 0x6789bb1d; | |
| imm32 r6, 0x7444d525; | |
| imm32 r7, 0x8666c747; | |
| R0.L = R2 + R0 (RND12); | |
| R1.L = R2 + R1 (RND12); | |
| R2.L = R2 + R2 (RND12); | |
| R3.L = R2 + R3 (RND12); | |
| R4.L = R2 + R4 (RND12); | |
| R5.L = R2 + R5 (RND12); | |
| R6.L = R2 + R6 (RND12); | |
| R7.L = R2 + R7 (RND12); | |
| CHECKREG r0, 0x55677fff; | |
| CHECKREG r1, 0x26897fff; | |
| CHECKREG r2, 0x3D447fff; | |
| CHECKREG r3, 0x46967fff; | |
| CHECKREG r4, 0xA67A8000; | |
| CHECKREG r5, 0x67897fff; | |
| CHECKREG r6, 0x74447fff; | |
| CHECKREG r7, 0x86668000; | |
| imm32 r0, 0xf5678901; | |
| imm32 r1, 0xd789ab7d; | |
| imm32 r2, 0x34445565; | |
| imm32 r3, 0xe6667757; | |
| imm32 r4, 0x5678894b; | |
| imm32 r5, 0x6d89ab3d; | |
| imm32 r6, 0x7444d525; | |
| imm32 r7, 0xe6667b77; | |
| R0.L = R3 + R0 (RND12); | |
| R1.L = R3 + R1 (RND12); | |
| R2.L = R3 + R2 (RND12); | |
| R3.L = R3 + R3 (RND12); | |
| R4.L = R3 + R4 (RND12); | |
| R5.L = R3 + R5 (RND12); | |
| R6.L = R3 + R6 (RND12); | |
| R7.L = R3 + R7 (RND12); | |
| CHECKREG r0, 0xF5678000; | |
| CHECKREG r1, 0xD7898000; | |
| CHECKREG r2, 0x34447FFF; | |
| CHECKREG r3, 0xE6668000; | |
| CHECKREG r4, 0x56787FFF; | |
| CHECKREG r5, 0x6D897FFF; | |
| CHECKREG r6, 0x74447FFF; | |
| CHECKREG r7, 0xE6668000; | |
| imm32 r0, 0xa5678911; | |
| imm32 r1, 0x2b89ab1d; | |
| imm32 r2, 0x34c45515; | |
| imm32 r3, 0x46d67717; | |
| imm32 r4, 0x56e8891b; | |
| imm32 r5, 0x67f9ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86687777; | |
| R0.L = R4 + R0 (RND12); | |
| R1.L = R4 + R1 (RND12); | |
| R2.L = R4 + R2 (RND12); | |
| R3.L = R4 + R3 (RND12); | |
| R4.L = R4 + R4 (RND12); | |
| R5.L = R4 + R5 (RND12); | |
| R6.L = R4 + R6 (RND12); | |
| R7.L = R4 + R7 (RND12); | |
| CHECKREG r0, 0xA567c501; | |
| CHECKREG r1, 0x2B897fff; | |
| CHECKREG r2, 0x34C47FFF; | |
| CHECKREG r3, 0x46D67FFF; | |
| CHECKREG r4, 0x56E87FFF; | |
| CHECKREG r5, 0x67F97FFF; | |
| CHECKREG r6, 0x74447FFF; | |
| CHECKREG r7, 0x86688000; | |
| imm32 r0, 0xe5678911; | |
| imm32 r1, 0x2789ab2d; | |
| imm32 r2, 0x34445535; | |
| imm32 r3, 0xd6667747; | |
| imm32 r4, 0x5ff8895b; | |
| imm32 r5, 0x6789ab8d; | |
| imm32 r6, 0x744e5515; | |
| imm32 r7, 0x8666a7b7; | |
| R0.L = R5 + R0 (RND12); | |
| R1.L = R5 + R1 (RND12); | |
| R2.L = R5 + R2 (RND12); | |
| R3.L = R5 + R3 (RND12); | |
| R4.L = R5 + R4 (RND12); | |
| R5.L = R5 + R5 (RND12); | |
| R6.L = R5 + R6 (RND12); | |
| R7.L = R5 + R7 (RND12); | |
| CHECKREG r0, 0xE5677FFF; | |
| CHECKREG r1, 0x27897FFF; | |
| CHECKREG r2, 0x34447FFF; | |
| CHECKREG r3, 0xD6667FFF; | |
| CHECKREG r4, 0x5FF87fff; | |
| CHECKREG r5, 0x67897FFF; | |
| CHECKREG r6, 0x744E7FFF; | |
| CHECKREG r7, 0x86668000; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ae1d; | |
| imm32 r2, 0x344455e5; | |
| imm32 r3, 0x4666771d; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789abdd; | |
| imm32 r6, 0x74a45515; | |
| imm32 r7, 0x866c77b7; | |
| R0.L = R6 + R0 (RND12); | |
| R1.L = R6 + R1 (RND12); | |
| R2.L = R6 + R2 (RND12); | |
| R3.L = R6 + R3 (RND12); | |
| R4.L = R6 + R4 (RND12); | |
| R5.L = R6 + R5 (RND12); | |
| R6.L = R6 + R6 (RND12); | |
| R7.L = R6 + R7 (RND12); | |
| CHECKREG r0, 0x15677FFF; | |
| CHECKREG r1, 0x27897FFF; | |
| CHECKREG r2, 0x34447FFF; | |
| CHECKREG r3, 0x46667FFF; | |
| CHECKREG r4, 0x56787FFF; | |
| CHECKREG r5, 0x67897FFF; | |
| CHECKREG r6, 0x74A47FFF; | |
| CHECKREG r7, 0x866Cb10f; | |
| imm32 r0, 0x25678931; | |
| imm32 r1, 0x2389ab14; | |
| imm32 r2, 0x34445576; | |
| imm32 r3, 0x46567787; | |
| imm32 r4, 0x5678899b; | |
| imm32 r5, 0x678dab1d; | |
| imm32 r6, 0x7444b515; | |
| imm32 r7, 0xb666a777; | |
| R0.L = R7 + R0 (RND12); | |
| R1.L = R7 + R1 (RND12); | |
| R2.L = R7 + R2 (RND12); | |
| R3.L = R7 + R3 (RND12); | |
| R4.L = R7 + R4 (RND12); | |
| R5.L = R7 + R5 (RND12); | |
| R6.L = R7 + R6 (RND12); | |
| R7.L = R7 + R7 (RND12); | |
| CHECKREG r0, 0x25678000; | |
| CHECKREG r1, 0x23898000; | |
| CHECKREG r2, 0x34448000; | |
| CHECKREG r3, 0x4656cbd2; | |
| CHECKREG r4, 0x56787FFF; | |
| CHECKREG r5, 0x678D7FFF; | |
| CHECKREG r6, 0x74447FFF; | |
| CHECKREG r7, 0xB6668000; | |
| imm32 r0, 0xaa678911; | |
| imm32 r1, 0x27ddab1d; | |
| imm32 r2, 0x344bb515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x56dd891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x7444bb15; | |
| imm32 r7, 0x86ff7777; | |
| R6.L = R2 + R3 (RND12); | |
| R1.L = R4 + R5 (RND12); | |
| R5.L = R7 + R2 (RND12); | |
| R3.L = R0 + R0 (RND12); | |
| R0.L = R3 + R4 (RND12); | |
| R2.L = R5 + R7 (RND12); | |
| R7.L = R6 + R7 (RND12); | |
| R4.L = R1 + R6 (RND12); | |
| CHECKREG r0, 0xAA677FFF; | |
| CHECKREG r1, 0x27DD7FFF; | |
| CHECKREG r2, 0x344B8000; | |
| CHECKREG r3, 0x46668000; | |
| CHECKREG r4, 0x56DD7FFF; | |
| CHECKREG r5, 0x67898000; | |
| CHECKREG r6, 0x74447FFF; | |
| CHECKREG r7, 0x86FFb43f; | |
| imm32 r0, 0x95678911; | |
| imm32 r1, 0x2d89ab1d; | |
| imm32 r2, 0x34b45515; | |
| imm32 r3, 0x46c67717; | |
| imm32 r4, 0x567e891b; | |
| imm32 r5, 0x678fab1d; | |
| imm32 r6, 0x744e5515; | |
| imm32 r7, 0x8b66a777; | |
| R3.L = R4 + R0 (RND12); | |
| R1.L = R6 + R3 (RND12); | |
| R4.L = R3 + R2 (RND12); | |
| R6.L = R7 + R1 (RND12); | |
| R2.L = R5 + R4 (RND12); | |
| R7.L = R2 + R7 (RND12); | |
| R0.L = R1 + R6 (RND12); | |
| R5.L = R0 + R5 (RND12); | |
| CHECKREG r0, 0x95677fff; | |
| CHECKREG r1, 0x2D897FFF; | |
| CHECKREG r2, 0x34B47FFF; | |
| CHECKREG r3, 0x46C68000; | |
| CHECKREG r4, 0x567E7FFF; | |
| CHECKREG r5, 0x678Fcf73; | |
| CHECKREG r6, 0x744E8000; | |
| CHECKREG r7, 0x8B668000; | |
| pass |