sim/testsuite/bfin/c_dsp32alu_rpm.s

//Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp
// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg)
# mach: bfin

.include "testutils.inc"
	start




// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.

imm32 r0, 0x65678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34845515;
imm32 r3, 0x46697717;
imm32 r4, 0x5567191b;
imm32 r5, 0x6789a31d;
imm32 r6, 0x74445545;
imm32 r7, 0x86667779;
R0 = R0 +|- R0;
R1 = R0 +|- R1;
R2 = R0 +|- R2;
R3 = R0 +|- R3;
R4 = R0 +|- R4;
R5 = R0 +|- R5;
R6 = R0 +|- R6;
R7 = R0 +|- R7;
CHECKREG r0, 0xCACE0000;
CHECKREG r1, 0xF25754E3;
CHECKREG r2, 0xFF52AAEB;
CHECKREG r3, 0x113788E9;
CHECKREG r4, 0x2035E6E5;
CHECKREG r5, 0x32575CE3;
CHECKREG r6, 0x3F12AABB;
CHECKREG r7, 0x51348887;

imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = R1 +|- R0;
R1 = R1 +|- R1;
R2 = R1 +|- R2;
R3 = R1 +|- R3;
R4 = R1 +|- R4;
R5 = R1 +|- R5;
R6 = R1 +|- R6;
R7 = R1 +|- R7;
CHECKREG r0, 0x3CF02202;
CHECKREG r1, 0x4F120000;
CHECKREG r2, 0x0356AADB;
CHECKREG r3, 0x157888D9;
CHECKREG r4, 0x279A66D7;
CHECKREG r5, 0x39BC44D5;
CHECKREG r6, 0x4BDE22D3;
CHECKREG r7, 0x5E000001;

imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = R2 +|- R0;
R1 = R2 +|- R1;
R2 = R2 +|- R2;
R3 = R2 +|- R3;
R4 = R2 +|- R4;
R5 = R2 +|- R5;
R6 = R2 +|- R6;
R7 = R2 +|- R7;
CHECKREG r0, 0x84ABCBAA;
CHECKREG r1, 0xA5CDA988;
CHECKREG r2, 0x86880000;
CHECKREG r3, 0xEAEE8889;
CHECKREG r4, 0xCBEF7655;
CHECKREG r5, 0xED115433;
CHECKREG r6, 0xCDCCAAAB;
CHECKREG r7, 0xEEEE8889;

imm32 r0, 0xa567892b;
imm32 r1, 0xaa89ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6a67727;
imm32 r0, 0x9a67892b;
imm32 r1, 0xa7a9ab2d;
imm32 r2, 0xb44a5525;
imm32 r3, 0xc666a727;
R0 = R3 +|- R0;
R1 = R3 +|- R1;
R2 = R3 +|- R2;
R3 = R3 +|- R3;
R4 = R3 +|- R4;
R5 = R3 +|- R5;
R6 = R3 +|- R6;
R7 = R3 +|- R7;
CHECKREG r0, 0x60CD1DFC;
CHECKREG r1, 0x6E0FFBFA;
CHECKREG r2, 0x7AB05202;
CHECKREG r3, 0x8CCC0000;
CHECKREG r4, 0x58BB89AB;
CHECKREG r5, 0x79DDABCD;
CHECKREG r6, 0x5A985555;
CHECKREG r7, 0x7BBA7777;

imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = R4 +|- R0;
R1 = R4 +|- R1;
R2 = R4 +|- R2;
R3 = R4 +|- R3;
R4 = R4 +|- R4;
R5 = R4 +|- R5;
R6 = R4 +|- R6;
R7 = R4 +|- R7;
CHECKREG r0, 0xCDAF0C4A;
CHECKREG r1, 0xEFD1EA38;
CHECKREG r2, 0xCCCD4030;
CHECKREG r3, 0xEEDE3E1E;
CHECKREG r4, 0x10F00000;
CHECKREG r5, 0xBB7A44A5;
CHECKREG r6, 0xDD8C227B;
CHECKREG r7, 0xFF9E0061;

imm32 r0, 0x456b89ab;
imm32 r1, 0x69764bcd;
imm32 r2, 0x49736564;
imm32 r3, 0x61278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = R5 +|- R0;
R1 = R5 +|- R1;
R2 = R5 +|- R2;
R3 = R5 +|- R3;
R4 = R5 +|- R4;
R5 = R5 +|- R5;
R6 = R5 +|- R6;
R7 = R5 +|- R7;
CHECKREG r0, 0xF0158210;
CHECKREG r1, 0x1420BFEE;
CHECKREG r2, 0xF41DA657;
CHECKREG r3, 0x0BD18827;
CHECKREG r4, 0x4331A782;
CHECKREG r5, 0x55540000;
CHECKREG r6, 0x2220E223;
CHECKREG r7, 0x67889001;

imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = R6 +|- R0;
R1 = R6 +|- R1;
R2 = R6 +|- R2;
R3 = R6 +|- R3;
R4 = R6 +|- R4;
R5 = R6 +|- R5;
R6 = R6 +|- R6;
R7 = R6 +|- R7;
CHECKREG r0, 0x4999572B;
CHECKREG r1, 0x6B9B4509;
CHECKREG r2, 0x07772981;
CHECKREG r3, 0x6A98295F;
CHECKREG r4, 0x16663A3D;
CHECKREG r5, 0x4999056B;
CHECKREG r6, 0x08640000;
CHECKREG r7, 0x1A98A981;

imm32 r0, 0xb76789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x2b456755;
imm32 r3, 0x56789007;
imm32 r4, 0x78bab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcdbff7;
R0 = R7 +|- R0;
R1 = R7 +|- R1;
R2 = R7 +|- R2;
R3 = R7 +|- R3;
R4 = R7 +|- R4;
R5 = R7 +|- R5;
R6 = R7 +|- R6;
R7 = R7 +|- R7;
CHECKREG r0, 0x6334364C;
CHECKREG r1, 0x1346142A;
CHECKREG r2, 0xD71258A2;
CHECKREG r3, 0x02452FF0;
CHECKREG r4, 0x2487085E;
CHECKREG r5, 0x5677B43C;
CHECKREG r6, 0x3578A27A;
CHECKREG r7, 0x579A0000;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = R4 +|- R7 (S);
R5 = R5 +|- R5 (CO);
R2 = R6 +|- R3 (SCO);
R6 = R0 +|- R4 (S);
R0 = R1 +|- R6 (S);
R2 = R2 +|- R1 (CO);
R1 = R3 +|- R0 (CO);
R7 = R7 +|- R4 (SCO);
CHECKREG r0, 0x7FFF123C;
CHECKREG r1, 0x553BE665;
CHECKREG r2, 0x1ECBE769;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x2468001A;
CHECKREG r5, 0x00008ACE;
CHECKREG r6, 0x69CF3991;
CHECKREG r7, 0x5665369C;

imm32 r0, 0xb76789ab;
imm32 r1, 0x6b79abcd;
imm32 r2, 0x2b456755;
imm32 r3, 0x56b89007;
imm32 r4, 0x78bab799;
imm32 r5, 0xaaab0bbb;
imm32 r6, 0x89abbd7d;
imm32 r7, 0xabcd2bf7;
R3 = R4 +|- R0 (S);
R5 = R5 +|- R1 (SCO);
R2 = R2 +|- R2 (S);
R7 = R7 +|- R3 (CO);
R4 = R3 +|- R4 (CO);
R0 = R1 +|- R5 (S);
R1 = R0 +|- R6 (SCO);
R6 = R6 +|- R7 (SCO);
CHECKREG r0, 0x7FFF95A9;
CHECKREG r1, 0xD82C09AA;
CHECKREG r2, 0x568A0000;
CHECKREG r3, 0x30212DEE;
CHECKREG r4, 0x7655A8DB;
CHECKREG r5, 0x5FEE1624;
CHECKREG r6, 0xE18F87B4;
CHECKREG r7, 0xFE09DBEE;


pass