| //Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp |
| // Spec Reference: dsp32shift align24 |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| imm32 r0, 0x00000001; |
| imm32 r1, 0x01000801; |
| imm32 r2, 0x08200802; |
| imm32 r3, 0x08030803; |
| imm32 r4, 0x08004804; |
| imm32 r5, 0x08000505; |
| imm32 r6, 0x08000866; |
| imm32 r7, 0x08000807; |
| R1 = ALIGN24 ( R1 , R0 ); |
| R2 = ALIGN24 ( R2 , R0 ); |
| R3 = ALIGN24 ( R3 , R0 ); |
| R4 = ALIGN24 ( R4 , R0 ); |
| R5 = ALIGN24 ( R5 , R0 ); |
| R6 = ALIGN24 ( R6 , R0 ); |
| R7 = ALIGN24 ( R7 , R0 ); |
| R0 = ALIGN24 ( R0 , R0 ); |
| CHECKREG r0, 0x00000100; |
| CHECKREG r1, 0x00080100; |
| CHECKREG r2, 0x20080200; |
| CHECKREG r3, 0x03080300; |
| CHECKREG r4, 0x00480400; |
| CHECKREG r5, 0x00050500; |
| CHECKREG r6, 0x00086600; |
| CHECKREG r7, 0x00080700; |
| |
| imm32 r0, 0x0900d001; |
| imm32 r1, 0x09000002; |
| imm32 r2, 0x09400002; |
| imm32 r3, 0x09100003; |
| imm32 r4, 0x09020004; |
| imm32 r5, 0x09003005; |
| imm32 r6, 0x09000406; |
| imm32 r7, 0x09000057; |
| R0 = ALIGN24 ( R0 , R1 ); |
| R2 = ALIGN24 ( R2 , R1 ); |
| R3 = ALIGN24 ( R3 , R1 ); |
| R4 = ALIGN24 ( R4 , R1 ); |
| R5 = ALIGN24 ( R5 , R1 ); |
| R6 = ALIGN24 ( R6 , R1 ); |
| R7 = ALIGN24 ( R7 , R1 ); |
| R1 = ALIGN24 ( R1 , R1 ); |
| CHECKREG r0, 0x00D00109; |
| CHECKREG r1, 0x00000209; |
| CHECKREG r2, 0x40000209; |
| CHECKREG r3, 0x10000309; |
| CHECKREG r4, 0x02000409; |
| CHECKREG r5, 0x00300509; |
| CHECKREG r6, 0x00040609; |
| CHECKREG r7, 0x00005709; |
| |
| |
| imm32 r0, 0x0a00e001; |
| imm32 r1, 0x0a00e001; |
| imm32 r2, 0x0a00000f; |
| imm32 r3, 0x0a400010; |
| imm32 r4, 0x0a05e004; |
| imm32 r5, 0x0a006005; |
| imm32 r6, 0x0a00e706; |
| imm32 r7, 0x0a00e087; |
| R0 = ALIGN24 ( R0 , R2 ); |
| R1 = ALIGN24 ( R1 , R2 ); |
| R3 = ALIGN24 ( R3 , R2 ); |
| R4 = ALIGN24 ( R4 , R2 ); |
| R5 = ALIGN24 ( R5 , R2 ); |
| R6 = ALIGN24 ( R6 , R2 ); |
| R7 = ALIGN24 ( R7 , R2 ); |
| R2 = ALIGN24 ( R2 , R2 ); |
| CHECKREG r0, 0x00E0010A; |
| CHECKREG r1, 0x00E0010A; |
| CHECKREG r2, 0x00000F0A; |
| CHECKREG r3, 0x4000100A; |
| CHECKREG r4, 0x05E0040A; |
| CHECKREG r5, 0x0060050A; |
| CHECKREG r6, 0x00E7060A; |
| CHECKREG r7, 0x00E0870A; |
| |
| imm32 r0, 0x2b00f001; |
| imm32 r1, 0x0300f001; |
| imm32 r2, 0x0b40f002; |
| imm32 r3, 0x0b050010; |
| imm32 r4, 0x0b006004; |
| imm32 r5, 0x0b00f705; |
| imm32 r6, 0x0b00f086; |
| imm32 r7, 0x0b00f009; |
| R0 = ALIGN24 ( R0 , R3 ); |
| R1 = ALIGN24 ( R1 , R3 ); |
| R2 = ALIGN24 ( R2 , R3 ); |
| R4 = ALIGN24 ( R4 , R3 ); |
| R5 = ALIGN24 ( R5 , R3 ); |
| R6 = ALIGN24 ( R6 , R3 ); |
| R7 = ALIGN24 ( R7 , R3 ); |
| R3 = ALIGN24 ( R3 , R3 ); |
| CHECKREG r0, 0x00F0010B; |
| CHECKREG r1, 0x00F0010B; |
| CHECKREG r2, 0x40F0020B; |
| CHECKREG r3, 0x0500100B; |
| CHECKREG r4, 0x0060040B; |
| CHECKREG r5, 0x00F7050B; |
| CHECKREG r6, 0x00F0860B; |
| CHECKREG r7, 0x00F0090B; |
| |
| imm32 r0, 0x4c0000c0; |
| imm32 r1, 0x050100c0; |
| imm32 r2, 0x0c6200c0; |
| imm32 r3, 0x0c0700c0; |
| imm32 r4, 0x0c04800c; |
| imm32 r5, 0x0c0509c0; |
| imm32 r6, 0x0c060000; |
| imm32 r7, 0x0c0700ca; |
| R0 = ALIGN24 ( R0 , R4 ); |
| R1 = ALIGN24 ( R1 , R4 ); |
| R2 = ALIGN24 ( R2 , R4 ); |
| R3 = ALIGN24 ( R3 , R4 ); |
| R5 = ALIGN24 ( R5 , R4 ); |
| R6 = ALIGN24 ( R6 , R4 ); |
| R7 = ALIGN24 ( R7 , R4 ); |
| R4 = ALIGN24 ( R4 , R4 ); |
| CHECKREG r0, 0x0000C00C; |
| CHECKREG r1, 0x0100C00C; |
| CHECKREG r2, 0x6200C00C; |
| CHECKREG r3, 0x0700C00C; |
| CHECKREG r4, 0x04800C0C; |
| CHECKREG r5, 0x0509C00C; |
| CHECKREG r6, 0x0600000C; |
| CHECKREG r7, 0x0700CA0C; |
| |
| imm32 r0, 0xa00100d0; |
| imm32 r1, 0xa00100d1; |
| imm32 r2, 0xa00200d0; |
| imm32 r3, 0xa00300d0; |
| imm32 r4, 0xa00400d0; |
| imm32 r5, 0xa0050007; |
| imm32 r6, 0xa00600d0; |
| imm32 r7, 0xa00700d0; |
| R0 = ALIGN24 ( R0 , R5 ); |
| R1 = ALIGN24 ( R1 , R5 ); |
| R2 = ALIGN24 ( R2 , R5 ); |
| R3 = ALIGN24 ( R3 , R5 ); |
| R4 = ALIGN24 ( R4 , R5 ); |
| R6 = ALIGN24 ( R6 , R5 ); |
| R7 = ALIGN24 ( R7 , R5 ); |
| R5 = ALIGN24 ( R5 , R5 ); |
| CHECKREG r0, 0x0100D0A0; |
| CHECKREG r1, 0x0100D1A0; |
| CHECKREG r2, 0x0200D0A0; |
| CHECKREG r3, 0x0300D0A0; |
| CHECKREG r4, 0x0400D0A0; |
| CHECKREG r5, 0x050007A0; |
| CHECKREG r6, 0x0600D0A0; |
| CHECKREG r7, 0x0700D0A0; |
| |
| imm32 r0, 0xb2010000; |
| imm32 r1, 0xb0310000; |
| imm32 r2, 0xb042000f; |
| imm32 r3, 0xbf030000; |
| imm32 r4, 0xba040000; |
| imm32 r5, 0xbb050000; |
| imm32 r6, 0xbc060009; |
| imm32 r7, 0xb0e70000; |
| R0 = ALIGN24 ( R0 , R6 ); |
| R1 = ALIGN24 ( R1 , R6 ); |
| R2 = ALIGN24 ( R2 , R6 ); |
| R3 = ALIGN24 ( R3 , R6 ); |
| R4 = ALIGN24 ( R4 , R6 ); |
| R5 = ALIGN24 ( R5 , R6 ); |
| R6 = ALIGN24 ( R6 , R6 ); |
| R7 = ALIGN24 ( R7 , R6 ); |
| CHECKREG r0, 0x010000BC; |
| CHECKREG r1, 0x310000BC; |
| CHECKREG r2, 0x42000FBC; |
| CHECKREG r3, 0x030000BC; |
| CHECKREG r4, 0x040000BC; |
| CHECKREG r5, 0x050000BC; |
| CHECKREG r6, 0x060009BC; |
| CHECKREG r7, 0xE7000006; |
| |
| imm32 r0, 0xd23100e0; |
| imm32 r1, 0xd04500e0; |
| imm32 r2, 0xde32f0e0; |
| imm32 r3, 0xd90300e0; |
| imm32 r4, 0xd07400e0; |
| imm32 r5, 0xdef500e0; |
| imm32 r6, 0xd06600e0; |
| imm32 r7, 0xd0080023; |
| R1 = ALIGN24 ( R0 , R7 ); |
| R2 = ALIGN24 ( R1 , R7 ); |
| R3 = ALIGN24 ( R2 , R7 ); |
| R4 = ALIGN24 ( R3 , R7 ); |
| R5 = ALIGN24 ( R4 , R7 ); |
| R6 = ALIGN24 ( R5 , R7 ); |
| R7 = ALIGN24 ( R6 , R7 ); |
| R0 = ALIGN24 ( R7 , R7 ); |
| CHECKREG r0, 0xD0D0D0D0; |
| CHECKREG r1, 0x3100E0D0; |
| CHECKREG r2, 0x00E0D0D0; |
| CHECKREG r3, 0xE0D0D0D0; |
| CHECKREG r4, 0xD0D0D0D0; |
| CHECKREG r5, 0xD0D0D0D0; |
| CHECKREG r6, 0xD0D0D0D0; |
| CHECKREG r7, 0xD0D0D0D0; |
| |
| |
| pass |
