sim/testsuite/bfin/c_regmv_imlb_dep_stall.s

//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp
// Spec Reference: regmv imlb-depepency  stall
# mach: bfin

.include "testutils.inc"
	start

// R-reg to I,M-reg to R-reg: stall
	imm32 r0, 0x00001110;
	imm32 r1, 0x00213330;
	imm32 r2, 0x04015550;
	imm32 r3, 0x06607770;
	imm32 r4, 0x08010990;
	imm32 r5, 0x0a01b0b0;
	imm32 r6, 0x0c01dd00;
	imm32 r7, 0x0e01f0f0;
	I0 = R0;
	R7 = I0;
	I1 = R1;
	R0 = I1;
	I2 = R2;
	R1 = I2;
	I3 = R3;
	R2 = I3;
	M0 = R4;
	R3 = M0;
	M1 = R5;
	R4 = M1;
	M2 = R6;
	R5 = M2;
	M3 = R7;
	R6 = M3;

	CHECKREG r0, 0x00213330;
	CHECKREG r1, 0x04015550;
	CHECKREG r2, 0x06607770;
	CHECKREG r3, 0x08010990;
	CHECKREG r4, 0x0A01B0B0;
	CHECKREG r5, 0x0C01DD00;
	CHECKREG r6, 0x00001110;
	CHECKREG r7, 0x00001110;

	R0 = M3;
	R1 = M2;
	R2 = M1;
	R3 = M0;
	R4 = I3;
	R5 = I2;
	R6 = I1;
	R7 = I0;
	CHECKREG r0, 0x00001110;
	CHECKREG r1, 0x0C01DD00;
	CHECKREG r2, 0x0A01B0B0;
	CHECKREG r3, 0x08010990;
	CHECKREG r4, 0x06607770;
	CHECKREG r5, 0x04015550;
	CHECKREG r6, 0x00213330;
	CHECKREG r7, 0x00001110;

// R-to-M,I and to P-reg: stall
	imm32 i0, 0x00001111;
	imm32 i1, 0x12213341;
	imm32 i2, 0x14415541;
	imm32 i3, 0x16617741;
	imm32 m0, 0x18819941;
	imm32 m1, 0x1aa1bb41;
	imm32 m2, 0x1cc1dd41;
	imm32 m3, 0x1ee1ff41;
	M0 = R0;
	R0 = M0;
	M1 = R1;
	P1 = M1;
	M2 = R2;
	P2 = M2;
	M3 = R3;
	P3 = M3;
	I0 = R4;
	P4 = I0;
	I1 = R5;
	P5 = I1;
	I2 = R6;
	SP = I2;
	I3 = R7;
	FP = I3;

	CHECKREG r0, 0x00001110;
	CHECKREG p1, 0x0C01DD00;
	CHECKREG p2, 0x0A01B0B0;
	CHECKREG p3, 0x08010990;
	CHECKREG p4, 0x06607770;
	CHECKREG p5, 0x04015550;
	CHECKREG sp, 0x00213330;
	CHECKREG fp, 0x00001110;
	R0 = M0;
	R1 = M1;
	R2 = M2;
	R3 = M3;
	R4 = I0;
	R5 = I1;
	R6 = I2;
	R7 = I3;
	CHECKREG r0, 0x00001110;
	CHECKREG r1, 0x0C01DD00;
	CHECKREG r2, 0x0A01B0B0;
	CHECKREG r3, 0x08010990;
	CHECKREG r4, 0x06607770;
	CHECKREG r5, 0x04015550;
	CHECKREG r6, 0x00213330;
	CHECKREG r7, 0x00001110;

// R-reg to L,B-reg to R-reg: stall
	imm32 r0, 0x20001112;
	imm32 r1, 0x22213332;
	imm32 r2, 0x21215552;
	imm32 r3, 0x21627772;
	imm32 r4, 0x21812992;
	imm32 r5, 0x21a1b2b2;
	imm32 r6, 0x21c1d222;
	imm32 r7, 0x21e1ff22;
	L0 = R1;
	R0 = L0;
	L1 = R2;
	R1 = L1;
	L2 = R3;
	R2 = L2;
	L3 = R4;
	R3 = L3;
	B0 = R5;
	R4 = B0;
	B1 = R6;
	R5 = B1;
	B2 = R7;
	R6 = B2;
	B3 = R0;
	R7 = B3;

	CHECKREG r0, 0x22213332;
	CHECKREG r1, 0x21215552;
	CHECKREG r2, 0x21627772;
	CHECKREG r3, 0x21812992;
	CHECKREG r4, 0x21A1B2B2;
	CHECKREG r5, 0x21C1D222;
	CHECKREG r6, 0x21E1FF22;
	CHECKREG r7, 0x22213332;

	R0 = L3;
	R1 = L2;
	R2 = L1;
	R3 = L0;
	R4 = B3;
	R5 = B2;
	R6 = B1;
	R7 = B0;
	CHECKREG r0, 0x21812992;
	CHECKREG r1, 0x21627772;
	CHECKREG r2, 0x21215552;
	CHECKREG r3, 0x22213332;
	CHECKREG r4, 0x22213332;
	CHECKREG r5, 0x21E1FF22;
	CHECKREG r6, 0x21C1D222;
	CHECKREG r7, 0x21A1B2B2;

// R-reg to L,B-reg to P-reg: stall
	imm32 r0, 0x50001115;
	imm32 r1, 0x51213335;
	imm32 r2, 0x51415555;
	imm32 r3, 0x51617775;
	imm32 r4, 0x51819995;
	imm32 r5, 0x51a1bbb5;
	imm32 r6, 0x51c1ddd5;
	imm32 r7, 0x51e1fff5;
	L0 = R1;
	R0 = L0;
	L1 = R2;
	SP = L1;
	L2 = R3;
	FP = L2;
	L3 = R4;
	P1 = L3;
	B0 = R5;
	P2 = B0;
	B1 = R6;
	P3 = B1;
	B2 = R7;
	P4 = B2;
	B3 = R0;
	P5 = B3;

	CHECKREG r0, 0x51213335;
	CHECKREG p1, 0x51819995;
	CHECKREG p2, 0x51A1BBB5;
	CHECKREG p3, 0x51C1DDD5;
	CHECKREG p4, 0x51E1FFF5;
	CHECKREG p5, 0x51213335;
	CHECKREG sp, 0x51415555;
	CHECKREG fp, 0x51617775;

	R0 = L3;
	R1 = L2;
	R2 = L1;
	R3 = L0;
	R4 = B3;
	R5 = B2;
	R6 = B1;
	R7 = B0;
	CHECKREG r0, 0x51819995;
	CHECKREG r1, 0x51617775;
	CHECKREG r2, 0x51415555;
	CHECKREG r3, 0x51213335;
	CHECKREG r4, 0x51213335;
	CHECKREG r5, 0x51E1FFF5;
	CHECKREG r6, 0x51C1DDD5;
	CHECKREG r7, 0x51A1BBB5;

// R-reg to I,M-reg to L,B-reg:  stall
	imm32 r0, 0x00001111;
	imm32 r1, 0x72213337;
	imm32 r2, 0x74415557;
	imm32 r3, 0x76617777;
	imm32 r4, 0x78819997;
	imm32 r5, 0x7aa1bbb7;
	imm32 r6, 0x7cc1ddd7;
	imm32 r7, 0x77e1fff7;
	I0 = R0;
	L0 = I0;
	I1 = R1;
	L1 = I1;
	I2 = R2;
	L2 = I2;
	I3 = R3;
	L3 = I3;
	M0 = R4;
	B0 = M0;
	M1 = R5;
	B1 = M1;
	M2 = R6;
	B2 = M2;
	M3 = R7;
	B3 = M3;

	R0 = L3;
	R1 = L2;
	R2 = L1;
	R3 = L0;
	R4 = B3;
	R5 = B2;
	R6 = B1;
	R7 = B0;
	CHECKREG r0, 0x76617777;
	CHECKREG r1, 0x74415557;
	CHECKREG r2, 0x72213337;
	CHECKREG r3, 0x00001111;
	CHECKREG r4, 0x77E1FFF7;
	CHECKREG r5, 0x7CC1DDD7;
	CHECKREG r6, 0x7AA1BBB7;
	CHECKREG r7, 0x78819997;

	R0 = M3;
	R1 = M2;
	R2 = M1;
	R3 = M0;
	R4 = I3;
	R5 = I2;
	R6 = I1;
	R7 = I0;
	CHECKREG r0, 0x77E1FFF7;
	CHECKREG r1, 0x7CC1DDD7;
	CHECKREG r2, 0x7AA1BBB7;
	CHECKREG r3, 0x78819997;
	CHECKREG r4, 0x76617777;
	CHECKREG r5, 0x74415557;
	CHECKREG r6, 0x72213337;
	CHECKREG r7, 0x00001111;

// R-reg to L,B-reg to I,M reg:  stall
	imm32 r0, 0x00001111;
	imm32 r1, 0x81213338;
	imm32 r2, 0x81415558;
	imm32 r3, 0x81617778;
	imm32 r4, 0x81819998;
	imm32 r5, 0x81a1bbb8;
	imm32 r6, 0x81c1ddd8;
	imm32 r7, 0x81e1fff8;
	L0 = R0;
	I0 = L0;
	L1 = R1;
	I1 = L1;
	L2 = R2;
	I2 = L2;
	L3 = R3;
	I3 = L3;
	B0 = R4;
	M0 = B0;
	B1 = R5;
	M1 = B1;
	B2 = R6;
	M2 = B2;
	B3 = R7;
	M3 = B3;

	R0 = M0;
	R1 = M1;
	R2 = M2;
	R3 = M3;
	R4 = I0;
	R5 = I1;
	R6 = I2;
	R7 = I3;
	CHECKREG r0, 0x81819998;
	CHECKREG r1, 0x81A1BBB8;
	CHECKREG r2, 0x81C1DDD8;
	CHECKREG r3, 0x81E1FFF8;
	CHECKREG r4, 0x00001111;
	CHECKREG r5, 0x81213338;
	CHECKREG r6, 0x81415558;
	CHECKREG r7, 0x81617778;

	R0 = L3;
	R1 = L2;
	R2 = L1;
	R3 = L0;
	R4 = B3;
	R5 = B2;
	R6 = B1;
	R7 = B0;
	CHECKREG r0, 0x81617778;
	CHECKREG r1, 0x81415558;
	CHECKREG r2, 0x81213338;
	CHECKREG r3, 0x00001111;
	CHECKREG r4, 0x81E1FFF8;
	CHECKREG r5, 0x81C1DDD8;
	CHECKREG r6, 0x81A1BBB8;
	CHECKREG r7, 0x81819998;

	pass