blob: 8ddfcaa33d05daed108194cf50c026cc0d0beb96 [file] [log] [blame]
# frv testcase for bcnlr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcnlr
bcnlr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x1 1
bcnlr icc1,0,1
set_spr_addr bad,lr
set_icc 0x2 2
bcnlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x3 3
bcnlr icc3,0,3
set_spr_addr bad,lr
set_icc 0x4 0
bcnlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x5 1
bcnlr icc1,0,1
set_spr_addr bad,lr
set_icc 0x6 2
bcnlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x7 3
bcnlr icc3,0,3
set_spr_addr ok9,lr
set_icc 0x8 0
bcnlr icc0,0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bcnlr icc1,0,1
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bcnlr icc2,0,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcnlr icc3,0,3
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
bcnlr icc0,0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bcnlr icc1,0,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bcnlr icc2,0,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bcnlr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bcnlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bcnlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bcnlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcnlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bcnlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcnlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bcnlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcnlr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcnlr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcnlr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcnlr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bcnlr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcnlr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bcnlr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcnlr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,1,0
set_icc 0x1 1
bcnlr icc1,1,1
set_icc 0x2 2
bcnlr icc2,1,2
set_icc 0x3 3
bcnlr icc3,1,3
set_icc 0x4 0
bcnlr icc0,1,0
set_icc 0x5 1
bcnlr icc1,1,1
set_icc 0x6 2
bcnlr icc2,1,2
set_icc 0x7 3
bcnlr icc3,1,3
set_icc 0x8 0
bcnlr icc0,1,0
set_icc 0x9 1
bcnlr icc1,1,1
set_icc 0xa 2
bcnlr icc2,1,2
set_icc 0xb 3
bcnlr icc3,1,3
set_icc 0xc 0
bcnlr icc0,1,0
set_icc 0xd 1
bcnlr icc1,1,1
set_icc 0xe 2
bcnlr icc2,1,2
set_icc 0xf 3
bcnlr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcnlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcnlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcnlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcnlr icc3,0,3
pass
bad:
fail