| # frv testcase for fcbnolr | |
| # mach: all | |
| .include "testutils.inc" | |
| start | |
| .global fcbnolr | |
| fcbnolr: | |
| ; ccond is true | |
| set_spr_immed 128,lcr | |
| set_spr_addr bad,lr | |
| set_fcc 0x0 0 | |
| fcbnolr | |
| set_fcc 0x1 1 | |
| fcbnolr | |
| set_fcc 0x2 2 | |
| fcbnolr | |
| set_fcc 0x3 3 | |
| fcbnolr | |
| set_fcc 0x4 0 | |
| fcbnolr | |
| set_fcc 0x5 1 | |
| fcbnolr | |
| set_fcc 0x6 2 | |
| fcbnolr | |
| set_fcc 0x7 3 | |
| fcbnolr | |
| set_fcc 0x8 0 | |
| fcbnolr | |
| set_fcc 0x9 1 | |
| fcbnolr | |
| set_fcc 0xa 2 | |
| fcbnolr | |
| set_fcc 0xb 3 | |
| fcbnolr | |
| set_fcc 0xc 0 | |
| fcbnolr | |
| set_fcc 0xd 1 | |
| fcbnolr | |
| set_fcc 0xe 2 | |
| fcbnolr | |
| set_fcc 0xf 3 | |
| fcbnolr | |
| ; ccond is true | |
| set_spr_immed 1,lcr | |
| set_fcc 0x0 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x1 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x2 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x3 3 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x4 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x5 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x6 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x7 3 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x8 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x9 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xa 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xb 3 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xc 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xd 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xe 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xf 3 | |
| fcbnolr | |
| ; ccond is false | |
| set_spr_immed 128,lcr | |
| set_fcc 0x0 0 | |
| fcbnolr | |
| set_fcc 0x1 1 | |
| fcbnolr | |
| set_fcc 0x2 2 | |
| fcbnolr | |
| set_fcc 0x3 3 | |
| fcbnolr | |
| set_fcc 0x4 0 | |
| fcbnolr | |
| set_fcc 0x5 1 | |
| fcbnolr | |
| set_fcc 0x6 2 | |
| fcbnolr | |
| set_fcc 0x7 3 | |
| fcbnolr | |
| set_fcc 0x8 0 | |
| fcbnolr | |
| set_fcc 0x9 1 | |
| fcbnolr | |
| set_fcc 0xa 2 | |
| fcbnolr | |
| set_fcc 0xb 3 | |
| fcbnolr | |
| set_fcc 0xc 0 | |
| fcbnolr | |
| set_fcc 0xd 1 | |
| fcbnolr | |
| set_fcc 0xe 2 | |
| fcbnolr | |
| set_fcc 0xf 3 | |
| fcbnolr | |
| ; ccond is false | |
| set_spr_immed 1,lcr | |
| set_fcc 0x0 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x1 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x2 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x3 3 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x4 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x5 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x6 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x7 3 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x8 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0x9 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xa 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xb 3 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xc 0 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xd 1 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xe 2 | |
| fcbnolr | |
| set_spr_immed 1,lcr | |
| set_fcc 0xf 3 | |
| fcbnolr | |
| pass | |
| bad: | |
| fail |