blob: 4d596b01b9f0a4d3db877c281774aa2355da95f0 [file] [log] [blame]
# frv testcase for tilt $ICCi_2,$GRi,$s12
# mach: all
.include "testutils.inc"
start
.global tilt
tilt:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 2112,gr7 ; address of exception handler
set_bctrlr_0_0 gr7 ; bctrlr 0,0
set_spr_immed 128,lcr
set_gr_immed 0,gr7
set_spr_addr bad,lr
set_icc 0x0 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
set_spr_addr bad,lr
set_icc 0x1 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
set_psr_et 1
set_spr_addr ok2,lr
set_icc 0x2 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
ok2:
set_psr_et 1
set_spr_addr ok3,lr
set_icc 0x3 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
ok3:
set_spr_addr bad,lr
set_icc 0x4 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
set_spr_addr bad,lr
set_icc 0x5 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
set_psr_et 1
set_spr_addr ok6,lr
set_icc 0x6 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
ok6:
set_psr_et 1
set_spr_addr ok7,lr
set_icc 0x7 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
ok7:
set_psr_et 1
set_spr_addr ok8,lr
set_icc 0x8 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
ok8:
set_psr_et 1
set_spr_addr ok9,lr
set_icc 0x9 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
ok9:
set_spr_addr bad,lr
set_icc 0xa 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
set_spr_addr bad,lr
set_icc 0xb 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
set_psr_et 1
set_spr_addr okc,lr
set_icc 0xc 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
okc:
set_psr_et 1
set_spr_addr okd,lr
set_icc 0xd 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
fail
okd:
set_spr_addr bad,lr
set_icc 0xe 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
set_spr_addr bad,lr
set_icc 0xf 0
tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16
pass
bad:
fail