)]}'
{
  "commit": "b0a101c53a1caa3f2a9fc2032f703ca4465cfbbb",
  "tree": "1f982cef3e1a4560c482629eece82363cea2f46f",
  "parents": [
    "7ab8bf1c777644f834ccbc5d1e83d721859ca1ba"
  ],
  "author": {
    "name": "Jiawei",
    "email": "jiawei@iscas.ac.cn",
    "time": "Wed Jul 12 20:40:36 2023 +0800"
  },
  "committer": {
    "name": "Nelson Chu",
    "email": "nelson@rivosinc.com",
    "time": "Tue Jul 18 11:45:58 2023 +0800"
  },
  "message": "RISC-V: Supports Zcb extension.\n\nThis patch support Zcb extension, contains new compressed instructions,\nsome instructions depend on other existed extension, like \u0027zba\u0027, \u0027zbb\u0027\nand \u0027zmmul\u0027.  Zcb also imply Zca extension to enable the compressing\nfeatures.\n\nCo-Authored by: Charlie Keaney \u003ccharlie.keaney@embecosm.com\u003e\nCo-Authored by: Mary Bennett \u003cmary.bennett@embecosm.com\u003e\nCo-Authored by: Nandni Jamnadas \u003cnandni.jamnadas@embecosm.com\u003e\nCo-Authored by: Sinan Lin \u003csinan.lin@linux.alibaba.com\u003e\nCo-Authored by: Simon Cook \u003csimon.cook@embecosm.com\u003e\nCo-Authored by: Shihua Liao \u003cshihua@iscas.ac.cn\u003e\nCo-Authored by: Yulong Shi \u003cyulong@iscas.ac.cn\u003e\n\nbfd/ChangeLog:\n\n        * elfxx-riscv.c (riscv_multi_subset_supports): New extension.\n        (riscv_multi_subset_supports_ext): Ditto.\n\ngas/ChangeLog:\n\n        * config/tc-riscv.c (validate_riscv_insn): New operators.\n        (riscv_ip): Ditto.\n        * testsuite/gas/riscv/zcb.d: New test.\n        * testsuite/gas/riscv/zcb.s: New test.\n\ninclude/ChangeLog:\n\n        * opcode/riscv-opc.h (MATCH_C_LBU): New opcode.\n        (MASK_C_LBU): New mask.\n        (MATCH_C_LHU): New opcode.\n        (MASK_C_LHU): New mask.\n        (MATCH_C_LH): New opcode.\n        (MASK_C_LH): New mask.\n        (MATCH_C_SB): New opcode.\n        (MASK_C_SB): New mask.\n        (MATCH_C_SH): New opcode.\n        (MASK_C_SH): New mask.\n        (MATCH_C_ZEXT_B): New opcode.\n        (MASK_C_ZEXT_B): New mask.\n        (MATCH_C_SEXT_B): New opcode.\n        (MASK_C_SEXT_B): New mask.\n        (MATCH_C_ZEXT_H): New opcode.\n        (MASK_C_ZEXT_H): New mask.\n        (MATCH_C_SEXT_H): New opcode.\n        (MASK_C_SEXT_H): New mask.\n        (MATCH_C_ZEXT_W): New opcode.\n        (MASK_C_ZEXT_W): New mask.\n        (MATCH_C_NOT): New opcode.\n        (MASK_C_NOT): New mask.\n        (MATCH_C_MUL): New opcode.\n        (MASK_C_MUL): New mask.\n        (DECLARE_INSN): New opcode.\n        * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func.\n        (EXTRACT_ZCB_HALFWORD_UIMM): Ditto.\n        (ENCODE_ZCB_BYTE_UIMM): Ditto.\n        (ENCODE_ZCB_HALFWORD_UIMM): Ditto.\n        (VALID_ZCB_BYTE_UIMM): Ditto.\n        (VALID_ZCB_HALFWORD_UIMM): Ditto.\n        (enum riscv_insn_class): New extension class.\n\nopcodes/ChangeLog:\n\n        * riscv-dis.c (print_insn_args): New operators.\n        * riscv-opc.c: New instructions.\n",
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