MIPS/opcodes: Replace "y" microMIPS operand code with "x" Replace the "y" microMIPS operand code, used with ALNV.PS only, with "x" so as to make "y" available for microMIPS MT use.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 1e4b3e2..67849ff 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h
@@ -1798,7 +1798,7 @@ (MICROMIPSOP_*_RS) "w" 5-bit same register used as both target and destination (MICROMIPSOP_*_RT) - "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) + "x" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) "z" must be zero register "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) @@ -1908,7 +1908,7 @@ "12345678 0" "<>(),+-.@\^|~" "ABCDEFGHI KLMN RST V " - "abcd fghijklmnopqrstuvw yz" + "abcd fghijklmnopqrstuvwx z" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more:
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index dca40a2..71595bf 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c
@@ -191,7 +191,7 @@ case 'u': HINT (16, 0); case 'v': OPTIONAL_REG (5, 16, GP); case 'w': OPTIONAL_REG (5, 21, GP); - case 'y': REG (5, 6, GP); + case 'x': REG (5, 6, GP); case 'z': MAPPED_REG (0, 0, GP, reg_0_map); } return 0; @@ -347,7 +347,7 @@ {"addu", "md,me,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, {"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{"alnv.ps", "D,V,T,x", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, {"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },