)]}'
{
  "commit": "b3a561abc3040264aa0c60a8082e2433b0ca38a1",
  "tree": "f173109e3ad0af7935e78b13b99f66ad6186ebe3",
  "parents": [
    "f9d6cf2e9f885a1504b459cf437dd9d1931b1168"
  ],
  "author": {
    "name": "Alex Coplan",
    "email": "alex.coplan@arm.com",
    "time": "Tue Apr 02 13:42:13 2024 +0100"
  },
  "committer": {
    "name": "Alex Coplan",
    "email": "alex.coplan@arm.com",
    "time": "Tue Apr 09 10:09:25 2024 +0100"
  },
  "message": "arm: Fix encoding of MVE vqshr[u]n\n\nAs it stands, these insns are incorrectly encoded as vqrshr[u]n.\nConcretely, the problem can be seen as follows:\n\n$ cat t.s\nvqrshrnb.s16 q0,q0,#8\nvqshrnb.s16 q0,q0,#8\n$ gas/as-new t.s -march\u003darmv8.1-m.main+mve -o t.o\n$ binutils/objdump -d t.o -m armv8.1-m.main\n\nt.o:     file format elf32-littlearm\n\nDisassembly of section .text:\n\n00000000 \u003c.text\u003e:\n   0:   ee88 0f41       vqrshrnb.s16    q0, q0, #0\n   4:   ee88 0f41       vqrshrnb.s16    q0, q0, #0\n\nHere we assemble these two instructions to the same opcode.  The\nencoding of the first is the correct, while the encoding of the second\nis incorrect, and the bottom bit should be clear, see the Armv8-M ARM:\nhttps://developer.arm.com/documentation/ddi0553/latest/\n\nThere is an additional problem here in that the disassembly of the\nimmediate is incorrect.  llvm-objdump shows the correct disassembly\nhere:\n\nt.o:    file format elf32-littlearm\n\nDisassembly of section .text:\n\n00000000 \u003c$t\u003e:\n       0: ee88 0f41     vqrshrnb.s16    q0, q0, #8\n       4: ee88 0f41     vqrshrnb.s16    q0, q0, #8\n\nNote that we defer adding a test for the correct encoding of these insns\nuntil the next patch which fixes the disassembly issue.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3bbb75c169abb7327d9cf6be0450a3fcf2267ff8",
      "old_mode": 33188,
      "old_path": "gas/config/tc-arm.c",
      "new_id": "89c85745adc53bed8e1c32783066b7f9df754fb1",
      "new_mode": 33188,
      "new_path": "gas/config/tc-arm.c"
    }
  ]
}