)]}'
{
  "commit": "b408ebbf526e7293f08825d04b34c7d2ad7fc753",
  "tree": "3331d54d3c7cafb02746194a07d78646b65f5c73",
  "parents": [
    "d8773a8a5f5614f508d9919cb7626ae0497b8141"
  ],
  "author": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:12 2023 +0100"
  },
  "committer": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:12 2023 +0100"
  },
  "message": "aarch64: Add the SME2 multivector LD1 and ST1 instructions\n\nSME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.\nThe registers can be consecutive or strided.  In the strided case,\n2-register lists have a stride of 8, starting at register x0xxx.\n4-register lists have a stride of 4, starting at register x00xx.\n\nThe instructions are predicated on a predicate-as-counter register in\nthe range pn8-pn15.  Although we already had register fields with upper\nbounds of 7 and 15, this is the first plain register operand to have a\nnonzero lower bound.  The patch uses the operand-specific data field\nto record the minimum value, rather than having separate inserters\nand extractors for each lower bound.  This in turn required adding\nan extra bit to the field.\n",
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