)]}'
{
  "commit": "b4681c2e8a46af1559990398bbc8f010d26312ca",
  "tree": "2654ae6fa5a28092e9add06565a152fddcd8edeb",
  "parents": [
    "1d458f0843141734b73f3a895dee73626fd85cb3"
  ],
  "author": {
    "name": "Monk Chiang",
    "email": "monk.chiang@sifive.com",
    "time": "Fri Jan 17 09:53:00 2025 +0800"
  },
  "committer": {
    "name": "Nelson Chu",
    "email": "nelson@rivosinc.com",
    "time": "Fri Jan 17 12:34:45 2025 +0800"
  },
  "message": "RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.\n\nhttps://github.com/riscv/riscv-cfi/releases/tag/v1.0\n\nThis patch only support the CFI instructions and CSR in assembler.\n",
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