)]}'
{
  "commit": "b625eff8a2346fe1107aa4ab7bbf4302f2c2136e",
  "tree": "9e11fce586187e074473ba6d38ea3e2be64c8697",
  "parents": [
    "15d842846d1fd79e141b1eddc9f648a8200223da"
  ],
  "author": {
    "name": "Philipp Tomsich",
    "email": "philipp.tomsich@vrull.eu",
    "time": "Tue Jun 27 07:22:49 2023 -0600"
  },
  "committer": {
    "name": "Jeff Law",
    "email": "jlaw@ventanamicro",
    "time": "Tue Jun 27 07:24:43 2023 -0600"
  },
  "message": "    RISC-V: Support Zicond extension\n\n    This implements the Zicond (conditional integer operations) extension,\n    as of version 1.0-rc2.\n\n    The Zicond extension acts as a building block for branchless sequences\n    including conditional-arithmetic, conditional-logic and\n    conditional-select/move.\n    The following instructions constitute Zicond:\n      - czero.eqz rd, rs1, rs2  \u003d\u003e  rd \u003d (rs2 \u003d\u003d 0) ? 0 : rs1\n      - czero.nez rd, rs1, rs2  \u003d\u003e  rd \u003d (rs2 !\u003d 0) ? 0 : rs1\n\n    See\n      https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf\n    for the proposed specification and usage details.\n\n    bfd/ChangeLog:\n\n            * elfxx-riscv.c (riscv_multi_subset_supports): Recognize\n            INSN_CLASS_ZICOND.\n            (riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND.\n\n    gas/ChangeLog:\n\n            * testsuite/gas/riscv/zicond.d: New test.\n            * testsuite/gas/riscv/zicond.s: New test.\n\n    include/ChangeLog:\n\n            * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.\n            (MASK_CZERO_EQZ): Define.\n            (MATCH_CZERO_NEZ): Define,\n            (MASK_CZERO_NEZ): Define.\n            (DECLARE_INSN): Add czero.eqz and czero.nez.\n            * opcode/riscv.h (enum riscv_insn_class): Add\n            INSN_CLASS_ZICOND.\n\n    opcodes/ChangeLog:\n\n            * riscv-opc.c: Add czero.eqz and czero.nez.\n\n    Signed-off-by: Philipp Tomsich \u003cphilipp.tomsich@vrull.eu\u003e\n",
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