Google Git
Sign in
gnu / binutils-gdb / b7ee8ec914c612587b080e9ad416315307f094fd / . / opcodes / csky-opc.h
blob: f8ff08af3fab9bd460ccb977bb85592a2d2e3f9e [file] [log] [blame]
<
/* Declarations for C-SKY opcode table
Copyright (C) 2007-2024 Free Software Foundation, Inc.
Contributed by C-SKY Microsystems and Mentor Graphics.
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include "opcode/csky.h"
#include "safe-ctype.h"
#define OP_TABLE_NUM 2
#define MAX_OPRND_NUM 5
enum operand_type
{
OPRND_TYPE_NONE = 0,
/* Control register. */
OPRND_TYPE_CTRLREG,
/* r0 - r7. */
OPRND_TYPE_GREG0_7,
/* r0 - r15. */
OPRND_TYPE_GREG0_15,
/* r16 - r31. */
OPRND_TYPE_GREG16_31,
/* r0 - r31. */
OPRND_TYPE_AREG,
/* (rx). */
OPRND_TYPE_AREG_WITH_BRACKET,
OPRND_TYPE_AREG_WITH_LSHIFT,
OPRND_TYPE_AREG_WITH_LSHIFT_FPU,
OPRND_TYPE_FREG_WITH_INDEX,
OPRND_TYPE_VREG_WITH_INDEX,
/* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */
OPRND_TYPE_REG_r1a,
/* r1 only, for divs/divu in csky v1 ISA. */
OPRND_TYPE_REG_r1b,
/* r28. */
OPRND_TYPE_REG_r28,
OPRND_TYPE_REGr4_r7,
/* sp register with bracket. */
OPRND_TYPE_REGbsp,
/* sp register. */
OPRND_TYPE_REGsp,
/* Register with bracket. */
OPRND_TYPE_REGnr4_r7,
/* Not sp register. */
OPRND_TYPE_REGnsp,
/* Not lr register. */
OPRND_TYPE_REGnlr,
/* Not sp/lr register. */
OPRND_TYPE_REGnsplr,
/* hi/lo register. */
OPRND_TYPE_REGhilo,
/* VDSP register. */
OPRND_TYPE_VREG,
/* cp index. */
OPRND_TYPE_CPIDX,
/* cp regs. */
OPRND_TYPE_CPREG,
/* cp cregs. */
OPRND_TYPE_CPCREG,
/* fpu regs. */
OPRND_TYPE_FREG,
/* fpu even regs. */
OPRND_TYPE_FEREG,
/* Float round mode. */
OPRND_TYPE_RM,
/* PSR bits. */
OPRND_TYPE_PSR_BITS_LIST,
/* Constant. */
OPRND_TYPE_CONSTANT,
/* Floating Constant. */
OPRND_TYPE_FCONSTANT,
/* Extern lrw constant. */
OPRND_TYPE_ELRW_CONSTANT,
/* [label]. */
OPRND_TYPE_LABEL_WITH_BRACKET,
/* The operand is the same as first reg. It is a dummy reg that doesn't
appear in the binary code of the instruction. It is also used by
the disassembler.
For example: bclri rz, rz, imm5 -> bclri rz, imm5. */
OPRND_TYPE_DUMMY_REG,
/* The type of the operand is same as the first operand. If the value
of the operand is same as the first operand, we can use a 16-bit
instruction to represent the opcode.
For example: addc r1, r1, r2 -> addc16 r1, r2. */
OPRND_TYPE_2IN1_DUMMY,
/* Output a reg same as the first reg.
For example: addc r17, r1 -> addc32 r17, r17, r1.
The old "addc" cannot be represented by a 16-bit instruction because
16-bit "addc" only supports regs from r0 to r15. So we use "addc32"
which has 3 operands, and duplicate the first operand to the second. */
OPRND_TYPE_DUP_GREG0_7,
OPRND_TYPE_DUP_GREG0_15,
OPRND_TYPE_DUP_AREG,
/* Immediate. */
OPRND_TYPE_IMM1b,
OPRND_TYPE_IMM2b,
OPRND_TYPE_IMM3b,
OPRND_TYPE_IMM4b,
OPRND_TYPE_IMM5b,
OPRND_TYPE_IMM7b,
OPRND_TYPE_IMM8b,
OPRND_TYPE_IMM9b,
OPRND_TYPE_IMM12b,
OPRND_TYPE_IMM15b,
OPRND_TYPE_IMM16b,
OPRND_TYPE_IMM18b,
OPRND_TYPE_IMM32b,
/* Immediate left shift 2 bits. */
OPRND_TYPE_IMM7b_LS2,
OPRND_TYPE_IMM8b_LS2,
/* OPRND_TYPE_IMM5b_a_b means: Immediate in (a, b). */
OPRND_TYPE_IMM5b_1_31,
OPRND_TYPE_IMM5b_7_31,
/* OPRND_TYPE_IMM5b_LS means: Imm <= prev Imm. */
OPRND_TYPE_IMM5b_LS,
/* Operand type for rori and rotri. */
OPRND_TYPE_IMM5b_RORI,
OPRND_TYPE_IMM5b_VSH,
OPRND_TYPE_IMM5b_POWER,
OPRND_TYPE_IMM5b_7_31_POWER,
OPRND_TYPE_IMM5b_BMASKI,
OPRND_TYPE_IMM8b_BMASKI,
/* For v2 movih. */
OPRND_TYPE_IMM16b_MOVIH,
/* For v2 ori. */
OPRND_TYPE_IMM16b_ORI,
/* For v2 ld/st. */
OPRND_TYPE_IMM_LDST,
OPRND_TYPE_IMM_FLDST,
OPRND_TYPE_IMM2b_JMPIX,
/* Offset for bloop. */
OPRND_TYPE_BLOOP_OFF4b,
OPRND_TYPE_BLOOP_OFF12b,
/* Offset for jump. */
OPRND_TYPE_OFF8b,
OPRND_TYPE_OFF10b,
OPRND_TYPE_OFF11b,
OPRND_TYPE_OFF16b,
OPRND_TYPE_OFF16b_LSL1,
OPRND_TYPE_OFF26b,
/* An immediate or label. */
OPRND_TYPE_IMM_OFF18b,
/* Offset immediate. */
OPRND_TYPE_OIMM3b,
OPRND_TYPE_OIMM4b,
OPRND_TYPE_OIMM5b,
OPRND_TYPE_OIMM8b,
OPRND_TYPE_OIMM12b,
OPRND_TYPE_OIMM16b,
OPRND_TYPE_OIMM18b,
/* For csky v2 idly. */
OPRND_TYPE_OIMM5b_IDLY,
/* For v2 bmaski. */
OPRND_TYPE_OIMM5b_BMASKI,
/* Constants. */
OPRND_TYPE_CONST1,
/* PC relative offset. */
OPRND_TYPE_PCR_OFFSET_16K,
OPRND_TYPE_PCR_OFFSET_64K,
OPRND_TYPE_PCR_OFFSET_64M,
OPRND_TYPE_CPFUNC,
OPRND_TYPE_GOT_PLT,
OPRND_TYPE_REGLIST_LDM,
OPRND_TYPE_REGLIST_DASH,
OPRND_TYPE_FREGLIST_DASH,
OPRND_TYPE_REGLIST_COMMA,
OPRND_TYPE_REGLIST_DASH_COMMA,
OPRND_TYPE_BRACKET,
OPRND_TYPE_ABRACKET,
OPRND_TYPE_JBTF,
OPRND_TYPE_JBR,
OPRND_TYPE_JBSR,
OPRND_TYPE_UNCOND10b,
OPRND_TYPE_UNCOND16b,
OPRND_TYPE_COND10b,
OPRND_TYPE_COND16b,
OPRND_TYPE_JCOMPZ,
OPRND_TYPE_LSB2SIZE,
OPRND_TYPE_MSB2SIZE,
OPRND_TYPE_LSB,
OPRND_TYPE_MSB,
/* Single float and double float. */
OPRND_TYPE_SFLOAT,
OPRND_TYPE_DFLOAT,
OPRND_TYPE_HFLOAT_FMOVI,
OPRND_TYPE_SFLOAT_FMOVI,
OPRND_TYPE_DFLOAT_FMOVI,
};
/* Operand descriptors. */
struct operand
{
/* Mask for suboperand. */
unsigned int mask;
/* Suboperand type. */
enum operand_type type;
/* Operand shift. */
int shift;
};
struct soperand
{
/* Mask for operand. */
unsigned int mask;
/* Operand type. */
enum operand_type type;
/* Operand shift. */
int shift;
/* Suboperand. */
struct operand subs[3];
};
union csky_operand
{
struct operand oprnds[MAX_OPRND_NUM];
struct suboperand1
{
struct operand oprnd;
struct soperand soprnd;
} soprnd1;
struct suboperand2
{
struct soperand soprnd;
struct operand oprnd;
} soprnd2;
};
/* Describe a single instruction encoding. */
struct csky_opcode_info
{
/* How many operands. */
long operand_num;
/* The instruction opcode. */
unsigned int opcode;
/* Operand information. */
union csky_operand oprnd;
};
/* C-SKY instruction description. Each mnemonic can have multiple
16-bit and 32-bit encodings. */
struct csky_opcode
{
/* The instruction name. */
const char *mnemonic;
/* Whether this is an unconditional control transfer instruction,
for the purposes of placing literal pools after it.
0 = no, 1 = within function, 2 = end of function.
See check_literals in gas/config/tc-csky.c. */
int transfer;
/* Encodings for 16-bit opcodes. */
struct csky_opcode_info op16[OP_TABLE_NUM];
/* Encodings for 32-bit opcodes. */
struct csky_opcode_info op32[OP_TABLE_NUM];
/* Instruction set flag. */
uint64_t isa_flag16;
uint64_t isa_flag32;
/* Whether this insn needs relocation, 0: no, !=0: yes. */
signed int reloc16;
signed int reloc32;
/* Whether this insn needs relaxation, 0: no, != 0: yes. */
signed int relax;
/* Worker function to call when this instruction needs special assembler
handling. */
bool (*work) (void);
};
/* The following are the opcodes used in relax/fix process. */
#define CSKYV1_INST_JMPI 0x7000
#define CSKYV1_INST_ADDI 0x2000
#define CSKYV1_INST_SUBI 0x2400
#define CSKYV1_INST_LDW 0x8000
#define CSKYV1_INST_STW 0x9000
#define CSKYV1_INST_BSR 0xf800
#define CSKYV1_INST_LRW 0x7000
#define CSKYV1_INST_ADDU 0x1c00
#define CSKYV1_INST_JMP 0x00c0
#define CSKYV1_INST_MOV_R1_RX 0x1201
#define CSKYV1_INST_MOV_RX_R1 0x1210
#define CSKYV2_INST_BT16 0x0800
#define CSKYV2_INST_BF16 0x0c00
#define CSKYV2_INST_BT32 0xe8600000
#define CSKYV2_INST_BF32 0xe8400000
#define CSKYV2_INST_BR32 0xe8000000
#define CSKYV2_INST_NOP 0x6c03
#define CSKYV2_INST_MOVI16 0x3000
#define CSKYV2_INST_MOVI32 0xea000000
#define CSKYV2_INST_MOVIH 0xea200000
#define CSKYV2_INST_LRW16 0x1000
#define CSKYV2_INST_LRW32 0xea800000
#define CSKYV2_INST_BSR32 0xe0000000
#define CSKYV2_INST_BR32 0xe8000000
#define CSKYV2_INST_FLRW 0xf4003800
#define CSKYV2_INST_JMPI32 0xeac00000
#define CSKYV2_INST_JSRI32 0xeae00000
#define CSKYV2_INST_JSRI_TO_LRW 0xea9a0000
#define CSKYV2_INST_JSR_R26 0xe8fa0000
#define CSKYV2_INST_MOV_R0_R0 0xc4004820
#define OPRND_SHIFT_0_BIT 0
#define OPRND_SHIFT_1_BIT 1
#define OPRND_SHIFT_2_BIT 2
#define OPRND_SHIFT_3_BIT 3
#define OPRND_SHIFT_4_BIT 4
#define OPRND_MASK_NONE 0x0
#define OPRND_MASK_0_1 0x3
#define OPRND_MASK_0_2 0x7
#define OPRND_MASK_0_3 0xf
#define OPRND_MASK_0_4 0x1f
#define OPRND_MASK_0_7 0xff
#define OPRND_MASK_0_8 0x1ff
#define OPRND_MASK_0_9 0x3ff
#define OPRND_MASK_0_10 0x7ff
#define OPRND_MASK_0_11 0xfff
#define OPRND_MASK_0_14 0x7fff
#define OPRND_MASK_0_15 0xffff
#define OPRND_MASK_0_17 0x3ffff
#define OPRND_MASK_0_25 0x3ffffff
#define OPRND_MASK_2_4 0x1c
#define OPRND_MASK_2_5 0x3c
#define OPRND_MASK_3_7 0xf8
#define OPRND_MASK_4 0x10
#define OPRND_MASK_4_5 0x30
#define OPRND_MASK_4_6 0x70
#define OPRND_MASK_4_7 0xf0
#define OPRND_MASK_4_8 0x1f0
#define OPRND_MASK_4_10 0x7f0
#define OPRND_MASK_5 0x20
#define OPRND_MASK_5_6 0x60
#define OPRND_MASK_5_7 0xe0
#define OPRND_MASK_5_8 0x1e0
#define OPRND_MASK_5_9 0x3e0
#define OPRND_MASK_6 0x40
#define OPRND_MASK_6_7 0xc0
#define OPRND_MASK_6_8 0x1c0
#define OPRND_MASK_6_9 0x3c0
#define OPRND_MASK_6_10 0x7c0
#define OPRND_MASK_7 0x80
#define OPRND_MASK_7_8 0x180
#define OPRND_MASK_8_9 0x300
#define OPRND_MASK_8_10 0x700
#define OPRND_MASK_8_11 0xf00
#define OPRND_MASK_9_10 0x600
#define OPRND_MASK_9_12 0x1e00
#define OPRND_MASK_10_11 0xc00
#define OPRND_MASK_10_14 0x7c00
#define OPRND_MASK_12_15 0xf000
#define OPRND_MASK_13_17 0x3e000
#define OPRND_MASK_16_19 0xf0000
#define OPRND_MASK_16_20 0x1f0000
#define OPRND_MASK_16_25 0x3ff0000
#define OPRND_MASK_17_24 0x1fe0000
#define OPRND_MASK_20 0x0100000
#define OPRND_MASK_20_21 0x0300000
#define OPRND_MASK_20_22 0x0700000
#define OPRND_MASK_20_23 0x0f00000
#define OPRND_MASK_20_24 0x1f00000
#define OPRND_MASK_20_25 0x3f00000
#define OPRND_MASK_21_24 0x1e00000
#define OPRND_MASK_21_25 0x3e00000
#define OPRND_MASK_25 0x2000000
#define OPRND_MASK_RSV 0xffffffff
#define OPRND_MASK_0_3or5_8 OPRND_MASK_0_3 | OPRND_MASK_5_8
#define OPRND_MASK_0_3or6_7 OPRND_MASK_0_3 | OPRND_MASK_6_7
#define OPRND_MASK_0_3or21_24 OPRND_MASK_0_3 | OPRND_MASK_21_24
#define OPRND_MASK_0_3or25 OPRND_MASK_0_3 | OPRND_MASK_25
#define OPRND_MASK_0_4or21_24 OPRND_MASK_0_4 | OPRND_MASK_21_24
#define OPRND_MASK_0_4or21_25 OPRND_MASK_0_4 | OPRND_MASK_21_25
#define OPRND_MASK_0_4or16_20 OPRND_MASK_0_4 | OPRND_MASK_16_20
#define OPRND_MASK_0_4or8_10 OPRND_MASK_0_4 | OPRND_MASK_8_10
#define OPRND_MASK_0_4or8_9 OPRND_MASK_0_4 | OPRND_MASK_8_9
#define OPRND_MASK_0_14or16_20 OPRND_MASK_0_14 | OPRND_MASK_16_20
#define OPRND_MASK_4or5_8 OPRND_MASK_4 | OPRND_MASK_5_8
#define OPRND_MASK_5or20_21 OPRND_MASK_5 | OPRND_MASK_20_21
#define OPRND_MASK_5or20_22 OPRND_MASK_5 | OPRND_MASK_20_22
#define OPRND_MASK_5or20_23 OPRND_MASK_5 | OPRND_MASK_20_23
#define OPRND_MASK_5or20_24 OPRND_MASK_5 | OPRND_MASK_20_24
#define OPRND_MASK_5or20_25 OPRND_MASK_5 | OPRND_MASK_20_25
#define OPRND_MASK_5or21_24 OPRND_MASK_5 | OPRND_MASK_21_24
#define OPRND_MASK_2_5or6_9 OPRND_MASK_2_5 | OPRND_MASK_6_9
#define OPRND_MASK_4_6or21_25 OPRND_MASK_4_6 | OPRND_MASK_21_25
#define OPRND_MASK_4_7or21_24 OPRND_MASK_4_7 | OPRND_MASK_21_24
#define OPRND_MASK_5_6or21_25 OPRND_MASK_5_6 | OPRND_MASK_21_25
#define OPRND_MASK_5_7or8_10 OPRND_MASK_5_7 | OPRND_MASK_8_10
#define OPRND_MASK_5_9or21_25 OPRND_MASK_5_9 | OPRND_MASK_21_25
#define OPRND_MASK_8_9or21_25 OPRND_MASK_8_9 | OPRND_MASK_21_25
#define OPRND_MASK_8_9or16_25 OPRND_MASK_8_9 | OPRND_MASK_16_20 | OPRND_MASK_21_25
#define OPRND_MASK_16_19or21_24 OPRND_MASK_16_19 | OPRND_MASK_21_24
#define OPRND_MASK_16_20or21_25 OPRND_MASK_16_20 | OPRND_MASK_21_25
#define OPRND_MASK_4or9_10or25 OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25
#define OPRND_MASK_4_7or16_24 OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24
#define OPRND_MASK_4_6or20 OPRND_MASK_4_6 | OPRND_MASK_20
#define OPRND_MASK_5_7or20 OPRND_MASK_5_7 | OPRND_MASK_20
#define OPRND_MASK_4_5or20or25 OPRND_MASK_4 | OPRND_MASK_5 | OPRND_MASK_20 | OPRND_MASK_25
#define OPRND_MASK_4_6or20or25 OPRND_MASK_4_6 | OPRND_MASK_20 | OPRND_MASK_25
#define OPRND_MASK_4_7or20or25 OPRND_MASK_4_7 | OPRND_MASK_20 | OPRND_MASK_25
#define OPRND_MASK_6_9or17_24 OPRND_MASK_6_9 | OPRND_MASK_17_24
#define OPRND_MASK_6_7or20 OPRND_MASK_6_7 | OPRND_MASK_20
#define OPRND_MASK_6or20 OPRND_MASK_6 | OPRND_MASK_20
#define OPRND_MASK_7or20 OPRND_MASK_7 | OPRND_MASK_20
#define OPRND_MASK_5or8_9or16_25 OPRND_MASK_5 | OPRND_MASK_8_9or16_25
#define OPRND_MASK_5or8_9or20_25 OPRND_MASK_5 | OPRND_MASK_8_9 | OPRND_MASK_20_25
#define OPERAND_INFO(mask, type, shift) \
{OPRND_MASK_##mask, OPRND_TYPE_##type, shift}
#define OPCODE_INFO_NONE() \
{-2, 0, \
{{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
/* Here and in subsequent macros, the "oprnd" arguments are the
parenthesized arglist to the OPERAND_INFO macro above. */
#define OPCODE_INFO(num, op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \
{num, op, \
{OPERAND_INFO oprnd1, OPERAND_INFO oprnd2, OPERAND_INFO oprnd3, \
OPERAND_INFO oprnd4, OPERAND_INFO oprnd5}}
#define OPCODE_INFO0(op) \
{0, op, \
{{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
#define OPCODE_INFO1(op, oprnd) \
{1, op, \
{{OPERAND_INFO oprnd, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
#define OPCODE_INFO2(op, oprnd1, oprnd2) \
{2, op, \
{{OPERAND_INFO oprnd1, \
OPERAND_INFO oprnd2, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
#define OPCODE_INFO3(op, oprnd1, oprnd2, oprnd3) \
{3, op, \
{{OPERAND_INFO oprnd1, \
OPERAND_INFO oprnd2, \
OPERAND_INFO oprnd3, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
#define OPCODE_INFO4(op, oprnd1, oprnd2, oprnd3, oprnd4) \
{4, op, \
{{OPERAND_INFO oprnd1, \
OPERAND_INFO oprnd2, \
OPERAND_INFO oprnd3, \
OPERAND_INFO oprnd4, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
#define OPCODE_INFO_LIST(op, oprnd) \
{-1, op, \
{{OPERAND_INFO oprnd, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) , \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
#define OPCODE_INFO5(op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \
{5, op, \
{{OPERAND_INFO oprnd1, \
OPERAND_INFO oprnd2, \
OPERAND_INFO oprnd3, \
OPERAND_INFO oprnd4, \
OPERAND_INFO oprnd5}}}
#define BRACKET_OPRND(oprnd1, oprnd2) \
OPERAND_INFO (RSV, BRACKET, OPRND_SHIFT_0_BIT), \
OPERAND_INFO oprnd1, \
OPERAND_INFO oprnd2, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)
#define ABRACKET_OPRND(oprnd1, oprnd2) \
OPERAND_INFO (RSV, ABRACKET, OPRND_SHIFT_0_BIT), \
OPERAND_INFO oprnd1, \
OPERAND_INFO oprnd2, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)
#define SOPCODE_INFO1(op, soprnd) \
{1, op, \
{{soprnd, \
OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}}
#define SOPCODE_INFO2(op, oprnd, soprnd) \
{2, op, \
{{OPERAND_INFO oprnd, soprnd}}}
/* Before using the opcode-defining macros, there need to be
#defines for _TRANSFER, _RELOC16, _RELOC32, and _RELAX. See
below. */
/* FIXME: it is a wart that these parameters are not explicit. */
#define OP16(mnem, opcode16, isa) \
{mnem, _TRANSFER, \
{opcode16, OPCODE_INFO_NONE ()}, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
isa, 0, _RELOC16, 0, _RELAX, NULL}
#ifdef BUILD_AS
#define OP16_WITH_WORK(mnem, opcode16, isa, work) \
{mnem, _TRANSFER, \
{opcode16, OPCODE_INFO_NONE ()}, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
isa, 0, _RELOC16, 0, _RELAX, work}
#define OP32_WITH_WORK(mnem, opcode32, isa, work) \
{mnem, _TRANSFER, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
{opcode32, OPCODE_INFO_NONE ()}, \
0, isa, 0, _RELOC32, _RELAX, work}
#define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \
{mnem, _TRANSFER, \
{opcode16, OPCODE_INFO_NONE ()}, \
{opcode32, OPCODE_INFO_NONE ()}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, work}
#define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \
{mnem, _TRANSFER, \
{opcode16a, opcode16b}, \
{opcode32, OPCODE_INFO_NONE ()}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, work}
#define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \
{mnem, _TRANSFER, \
{opcode16a, opcode16b}, \
{opcode32a, opcode32b}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, work}
#define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \
{mnem, _TRANSFER, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
{opcode32a, opcode32b}, \
0, isa, 0, _RELOC32, _RELAX, work}
#else /* ifdef BUILD_AS */
#define OP16_WITH_WORK(mnem, opcode16, isa, work) \
{mnem, _TRANSFER, \
{opcode16, OPCODE_INFO_NONE ()}, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
isa, 0, _RELOC16, 0, _RELAX, NULL}
#define OP32_WITH_WORK(mnem, opcode32, isa, work) \
{mnem, _TRANSFER, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
{opcode32, OPCODE_INFO_NONE ()}, \
0, isa, 0, _RELOC32, _RELAX, NULL}
#define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \
{mnem, _TRANSFER, \
{opcode16, OPCODE_INFO_NONE ()}, \
{opcode32, OPCODE_INFO_NONE ()}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL}
#define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \
{mnem, _TRANSFER, \
{opcode16a, opcode16b}, \
{opcode32, OPCODE_INFO_NONE ()}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL}
#define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \
{mnem, _TRANSFER, \
{opcode16a, opcode16b}, \
{opcode32a, opcode32b}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL}
#define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \
{mnem, _TRANSFER, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
{opcode32a, opcode32b}, \
0, isa, 0, _RELOC32, _RELAX, NULL}
#endif /* ifdef BUILD_AS */
#define DOP16(mnem, opcode16_1, opcode16_2, isa) \
{mnem, _TRANSFER, \
{opcode16_1, opcode16_2}, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
isa, 0, _RELOC16, 0, _RELAX, NULL}
#define OP32(mnem, opcode32, isa) \
{mnem, _TRANSFER, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
{opcode32, OPCODE_INFO_NONE ()}, \
0, isa, 0, _RELOC32, _RELAX, NULL}
#define DOP32(mnem, opcode32a, opcode32b, isa) \
{mnem, _TRANSFER, \
{OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \
{opcode32a, opcode32b}, \
0, isa, 0, _RELOC32, _RELAX, NULL}
#define OP16_OP32(mnem, opcode16, isa16, opcode32, isa32) \
{mnem, _TRANSFER, \
{opcode16, OPCODE_INFO_NONE ()}, \
{opcode32, OPCODE_INFO_NONE ()}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL}
#define DOP16_OP32(mnem, opcode16a, opcode16b, isa16, opcode32, isa32) \
{mnem, _TRANSFER, \
{opcode16a, opcode16b}, \
{opcode32, OPCODE_INFO_NONE ()}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL}
#define OP16_DOP32(mnem, opcode16, isa16, opcode32a, opcode32b, isa32) \
{mnem, _TRANSFER, \
{opcode16, OPCODE_INFO_NONE ()}, \
{opcode32a, opcode32b}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL}
#define DOP16_DOP32(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32) \
{mnem, _TRANSFER, \
{opcode16a, opcode16b}, \
{opcode32a, opcode32b}, \
isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL}
/* Register names and numbers. */
#define V1_REG_SP 0
#define V1_REG_LR 15
struct psrbit
{
int value;
int isa;
const char *name;
};
const struct psrbit cskyv1_psr_bits[] =
{
{1, 0, "ie"},
{2, 0, "fe"},
{4, 0, "ee"},
{8, 0, "af"},
{0, 0, NULL},
};
const struct psrbit cskyv2_psr_bits[] =
{
{8, 0, "ee"},
{4, 0, "ie"},
{2, 0, "fe"},
{1, 0, "af"},
{0x10, CSKY_ISA_TRUST, "sie"},
{0, 0, NULL},
};
#define GENERAL_REG_BANK 0x80000000
#define REG_SUPPORT_ALL 0xffffffff
/* CSKY register description. */
struct csky_reg_def
{
/* The group number for control registers,
and set the bank of genaral registers to a special number. */
int bank;
int regno;
/* The name displayed by serial number. */
const char *name;
/* The name displayed by ABI infomation,
used when objdump add option -Mabi-names. */
const char *abi_name;
/* The flags indicate which arches support the register. */
int arch_flag;
/* Some registers depend on special features. */
char *features;
};
/* Arch flag. */
#define ASH(a) (1 << CSKY_ARCH_##a)
/* All arches exclued 801. */
#define REG_SUPPORT_A (REG_SUPPORT_ALL & ~ASH(801))
/* All arches exclued 801 and 802. */
#define REG_SUPPORT_B (REG_SUPPORT_ALL & ~(ASH(801) | ASH(802)))
/* All arches exclued 801, 802, 803, 805.*/
#define REG_SUPPORT_C (REG_SUPPORT_ALL & ~(ASH(801) \
| ASH(802) | ASH(803) | ASH(805)))
/* All arches exclued 801, 802, 803, 805, 807, 810. */
#define REG_SUPPORT_D (REG_SUPPORT_C & ~(ASH(807) | ASH(810)))
/* All arches exclued 807, 810, 860. */
#define REG_SUPPORT_E (REG_SUPPORT_ALL & ~(ASH(807) | ASH(810) | \
ASH(860)))
/* C-SKY V1 general registers table. */
static struct csky_reg_def csky_abiv1_general_regs[] =
{
#define DECLARE_REG(regno, abi_name, support) \
{GENERAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL}
DECLARE_REG (0, "sp", REG_SUPPORT_ALL),
DECLARE_REG (1, NULL, REG_SUPPORT_ALL),
DECLARE_REG (2, "a0", REG_SUPPORT_ALL),
DECLARE_REG (3, "a1", REG_SUPPORT_ALL),
DECLARE_REG (4, "a2", REG_SUPPORT_ALL),
DECLARE_REG (5, "a3", REG_SUPPORT_ALL),
DECLARE_REG (6, "a4", REG_SUPPORT_ALL),
DECLARE_REG (7, "a5", REG_SUPPORT_ALL),
DECLARE_REG (8, "fp", REG_SUPPORT_ALL),
DECLARE_REG (8, "l0", REG_SUPPORT_ALL),
DECLARE_REG (9, "l1", REG_SUPPORT_ALL),
DECLARE_REG (10, "l2", REG_SUPPORT_ALL),
DECLARE_REG (11, "l3", REG_SUPPORT_ALL),
DECLARE_REG (12, "l4", REG_SUPPORT_ALL),
DECLARE_REG (13, "l5", REG_SUPPORT_ALL),
DECLARE_REG (14, "gb", REG_SUPPORT_ALL),
DECLARE_REG (15, "lr", REG_SUPPORT_ALL),
#undef DECLARE_REG
{-1, -1, NULL, NULL, 0, NULL},
};
/* C-SKY V1 control registers table. */
static struct csky_reg_def csky_abiv1_control_regs[] =
{
#define DECLARE_REG(regno, abi_name, support) \
{0, regno, "cr"#regno, abi_name, support, NULL}
DECLARE_REG (0, "psr", REG_SUPPORT_ALL),
DECLARE_REG (1, "vbr", REG_SUPPORT_ALL),
DECLARE_REG (2, "epsr", REG_SUPPORT_ALL),
DECLARE_REG (3, "fpsr", REG_SUPPORT_ALL),
DECLARE_REG (4, "epc", REG_SUPPORT_ALL),
DECLARE_REG (5, "fpc", REG_SUPPORT_ALL),
DECLARE_REG (6, "ss0", REG_SUPPORT_ALL),
DECLARE_REG (7, "ss1", REG_SUPPORT_ALL),
DECLARE_REG (8, "ss2", REG_SUPPORT_ALL),
DECLARE_REG (9, "ss3", REG_SUPPORT_ALL),
DECLARE_REG (10, "ss4", REG_SUPPORT_ALL),
DECLARE_REG (11, "gcr", REG_SUPPORT_ALL),
DECLARE_REG (12, "gsr", REG_SUPPORT_ALL),
DECLARE_REG (13, "cpid", REG_SUPPORT_ALL),
DECLARE_REG (14, "dcsr", REG_SUPPORT_ALL),
DECLARE_REG (15, "cwr", REG_SUPPORT_ALL),
DECLARE_REG (16, NULL, REG_SUPPORT_ALL),
DECLARE_REG (17, "cfr", REG_SUPPORT_ALL),
DECLARE_REG (18, "ccr", REG_SUPPORT_ALL),
DECLARE_REG (19, "capr", REG_SUPPORT_ALL),
DECLARE_REG (20, "pacr", REG_SUPPORT_ALL),
DECLARE_REG (21, "prsr", REG_SUPPORT_ALL),
DECLARE_REG (22, "mir", REG_SUPPORT_ALL),
DECLARE_REG (23, "mrr", REG_SUPPORT_ALL),
DECLARE_REG (24, "mel0", REG_SUPPORT_ALL),
DECLARE_REG (25, "mel1", REG_SUPPORT_ALL),
DECLARE_REG (26, "meh", REG_SUPPORT_ALL),
DECLARE_REG (27, "mcr", REG_SUPPORT_ALL),
DECLARE_REG (28, "mpr", REG_SUPPORT_ALL),
DECLARE_REG (29, "mwr", REG_SUPPORT_ALL),
DECLARE_REG (30, "mcir", REG_SUPPORT_ALL),
#undef DECLARE_REG
{-1, -1, NULL, NULL, 0, NULL},
};
/* C-SKY V2 general registers table. */
static struct csky_reg_def csky_abiv2_general_regs[] =
{
#ifdef DECLARE_REG
#undef DECLARE_REG
#endif
#define DECLARE_REG(regno, abi_name, support) \
{GENERAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL}
DECLARE_REG (0, "a0", REG_SUPPORT_ALL),
DECLARE_REG (1, "a1", REG_SUPPORT_ALL),
DECLARE_REG (2, "a2", REG_SUPPORT_ALL),
DECLARE_REG (3, "a3", REG_SUPPORT_ALL),
DECLARE_REG (4, "l0", REG_SUPPORT_ALL),
DECLARE_REG (5, "l1", REG_SUPPORT_ALL),
DECLARE_REG (6, "l2", REG_SUPPORT_ALL),
DECLARE_REG (7, "l3", REG_SUPPORT_ALL),
DECLARE_REG (8, "l4", REG_SUPPORT_ALL),
DECLARE_REG (9, "l5", REG_SUPPORT_A),
DECLARE_REG (10, "l6", REG_SUPPORT_A),
DECLARE_REG (11, "l7", REG_SUPPORT_A),
DECLARE_REG (12, "t0", REG_SUPPORT_A),
DECLARE_REG (13, "t1", REG_SUPPORT_ALL),
DECLARE_REG (14, "sp", REG_SUPPORT_ALL),
DECLARE_REG (15, "lr", REG_SUPPORT_ALL),
DECLARE_REG (16, "l8", REG_SUPPORT_B),
DECLARE_REG (17, "l9", REG_SUPPORT_B),
DECLARE_REG (18, "t2", REG_SUPPORT_B),
DECLARE_REG (19, "t3", REG_SUPPORT_B),
DECLARE_REG (20, "t4", REG_SUPPORT_B),
DECLARE_REG (21, "t5", REG_SUPPORT_B),
DECLARE_REG (22, "t6", REG_SUPPORT_B),
DECLARE_REG (23, "t7", REG_SUPPORT_B),
DECLARE_REG (24, "t8", REG_SUPPORT_B),
DECLARE_REG (25, "t9", REG_SUPPORT_B),
DECLARE_REG (26, NULL, REG_SUPPORT_B),
DECLARE_REG (27, NULL, REG_SUPPORT_B),
DECLARE_REG (28, "gb", REG_SUPPORT_B),
DECLARE_REG (28, "rgb", REG_SUPPORT_B),
DECLARE_REG (28, "rdb", REG_SUPPORT_B),
DECLARE_REG (29, "tb", REG_SUPPORT_B),
DECLARE_REG (29, "rtb", REG_SUPPORT_B),
DECLARE_REG (30, "svbr", REG_SUPPORT_A),
DECLARE_REG (31, "tls", REG_SUPPORT_B),
/* The followings JAVA/BCTM's features. */
DECLARE_REG (23, "fp", REG_SUPPORT_ALL),
DECLARE_REG (24, "top", REG_SUPPORT_ALL),
DECLARE_REG (25, "bsp", REG_SUPPORT_ALL),
{-1, -1, NULL, NULL, 0, NULL},
};
/* C-SKY V2 control registers table. */
static struct csky_reg_def csky_abiv2_control_regs[] =
{
#ifdef DECLARE_REG
#undef DECLARE_REG
#endif
/* Bank0. */
#define DECLARE_REG(regno, abi_name) \
{0, regno, "cr<"#regno", 0>", abi_name, REG_SUPPORT_ALL, NULL}
DECLARE_REG (0, "psr"),
DECLARE_REG (1, "vbr"),
DECLARE_REG (2, "epsr"),
DECLARE_REG (3, "fpsr"),
DECLARE_REG (4, "epc"),
DECLARE_REG (5, "fpc"),
DECLARE_REG (6, "ss0"),
DECLARE_REG (7, "ss1"),
DECLARE_REG (8, "ss2"),
DECLARE_REG (9, "ss3"),
DECLARE_REG (10, "ss4"),
DECLARE_REG (11, "gcr"),
DECLARE_REG (12, "gsr"),
DECLARE_REG (13, "cpid"),
DECLARE_REG (14, "dcsr"),
DECLARE_REG (15, NULL),
DECLARE_REG (16, NULL),
DECLARE_REG (17, "cfr"),
DECLARE_REG (18, "ccr"),
DECLARE_REG (19, "capr"),
DECLARE_REG (20, "pacr"),
DECLARE_REG (21, "prsr"),
DECLARE_REG (22, "cir"),
DECLARE_REG (23, "ccr2"),
DECLARE_REG (24, NULL),
DECLARE_REG (25, "cer2"),
DECLARE_REG (26, NULL),
DECLARE_REG (27, NULL),
DECLARE_REG (28, "rvbr"),
DECLARE_REG (29, "rmr"),
DECLARE_REG (30, "mpid"),
#undef DECLARE_REG
#define DECLARE_REG(regno, abi_name, support) \
{0, regno, "cr<"#regno", 0>", abi_name, support, NULL}
DECLARE_REG (31, "chr", REG_SUPPORT_E),
DECLARE_REG (31, "hint", REG_SUPPORT_C),
/* Bank1. */
#undef DECLARE_REG
#define DECLARE_REG(regno, abi_name) \
{1, regno, "cr<"#regno", 1>", abi_name, REG_SUPPORT_ALL, NULL}
DECLARE_REG (14, "usp"),
DECLARE_REG (26, "cindex"),
DECLARE_REG (27, "cdata0"),
DECLARE_REG (28, "cdata1"),
DECLARE_REG (29, "cdata2"),
DECLARE_REG (30, "cdata3"),
DECLARE_REG (31, "cins"),
/* Bank2. */
#undef DECLARE_REG
#define DECLARE_REG(regno, abi_name) \
{2, regno, "cr<"#regno", 2>", abi_name, REG_SUPPORT_ALL, NULL}
DECLARE_REG (0, "fid"),
DECLARE_REG (1, "fcr"),
DECLARE_REG (2, "fesr"),
/* Bank3. */
#undef DECLARE_REG
#define DECLARE_REG(regno, abi_name) \
{3, regno, "cr<"#regno", 3>", abi_name, REG_SUPPORT_ALL, NULL}
DECLARE_REG (8, "dcr"),
DECLARE_REG (8, "sedcr"),
DECLARE_REG (9, "pcr"),
DECLARE_REG (9, "sepcr"),
/* Bank15. */
#undef DECLARE_REG
#define DECLARE_REG(regno, abi_name) \
{15, regno, "cr<"#regno", 15>", abi_name, REG_SUPPORT_ALL, NULL}
DECLARE_REG (0, "mir"),
DECLARE_REG (2, "mel0"),
DECLARE_REG (3, "mel1"),
DECLARE_REG (4, "meh"),
DECLARE_REG (6, "mpr"),
DECLARE_REG (8, "mcir"),
DECLARE_REG (28, "mpgd0"),
DECLARE_REG (29, "mpgd"),
DECLARE_REG (29, "mpgd1"),
DECLARE_REG (30, "msa0"),
DECLARE_REG (31, "msa1"),
#undef DECLARE_REG
{-1, -1, NULL, NULL, 0, NULL},
};
/* Get register name according to giving parameters,
IS_ABI controls whether is ABI name or not. */
static inline const char *
get_register_name (struct csky_reg_def *reg_table,
int arch, int bank, int regno, int is_abi)
{
static char regname[64] = {0};
unsigned int i = 0;
while (reg_table[i].name != NULL)
{
if (reg_table[i].bank == bank
&& reg_table[i].regno == regno
&& (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK))))
{
if (is_abi && reg_table[i].abi_name)
return reg_table[i].abi_name;
else
return reg_table[i].name;
}
i++;
}
if (bank & 0x80000000)
return "unkown register";
sprintf (regname, "cr<%d, %d>", regno, bank);
return regname;
}
/* Get register number according to giving parameters.
If not found, return -1. */
static inline int
get_register_number (struct csky_reg_def *reg_table,
int arch, char *s, char **end, int *bank)
{
unsigned int i = 0;
int len = 0;
while (reg_table[i].name != NULL)
{
len = strlen (reg_table[i].name);
if ((strncasecmp (reg_table[i].name, s, len) == 0)
&& !(ISDIGIT (s[len]))
&& (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK))))
{
*end = s + len;
*bank = reg_table[i].bank;
return reg_table[i].regno;
}
if (reg_table[i].abi_name == NULL)
{
i++;
continue;
}
len = strlen (reg_table[i].abi_name);
if ((strncasecmp (reg_table[i].abi_name, s, len) == 0)
&& !(ISALNUM (s[len]))
&& (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK))))
{
*end = s + len;
*bank = reg_table[i].bank;
return reg_table[i].regno;
}
i++;
}
return -1;
}
/* Return general register's name. */
static inline const char *
csky_get_general_reg_name (int arch, int regno, int is_abi)
{
struct csky_reg_def *reg_table;
if (IS_CSKY_ARCH_V1 (arch))
reg_table = csky_abiv1_general_regs;
else
reg_table = csky_abiv2_general_regs;
return get_register_name (reg_table, arch, GENERAL_REG_BANK, regno, is_abi);
}
/* Return general register's number. */
static inline int
csky_get_general_regno (int arch, char *s, char **end)
{
struct csky_reg_def *reg_table;
int bank = 0;
if (IS_CSKY_ARCH_V1 (arch))
reg_table = csky_abiv1_general_regs;
else
reg_table = csky_abiv2_general_regs;
return get_register_number (reg_table, arch, s, end, &bank);
}
/* Return control register's name. */
static inline const char *
csky_get_control_reg_name (int arch, int bank, int regno, int is_abi)
{
struct csky_reg_def *reg_table;
if (IS_CSKY_ARCH_V1 (arch))
reg_table = csky_abiv1_control_regs;
else
reg_table = csky_abiv2_control_regs;
return get_register_name (reg_table, arch, bank, regno, is_abi);
}
/* Return control register's number. */
static inline int
csky_get_control_regno (int arch, char *s, char **end, int *bank)
{
struct csky_reg_def *reg_table;
if (IS_CSKY_ARCH_V1 (arch))
reg_table = csky_abiv1_control_regs;
else
reg_table = csky_abiv2_control_regs;
return get_register_number (reg_table, arch, s, end, bank);
}
/* C-SKY V1 opcodes. */
const struct csky_opcode csky_v1_opcodes[] =
{
#define _TRANSFER 0
#define _RELOC16 0
#define _RELOC32 0
#define _RELAX 0
OP16 ("bkpt",
OPCODE_INFO0 (0x0000),
CSKYV1_ISA_E1),
OP16 ("sync",
OPCODE_INFO0 (0x0001),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 2
OP16 ("rfi",
OPCODE_INFO0 (0x0003),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 0
OP16 ("stop",
OPCODE_INFO0 (0x0004),
CSKYV1_ISA_E1),
OP16 ("wait",
OPCODE_INFO0 (0x0005),
CSKYV1_ISA_E1),
OP16 ("doze",
OPCODE_INFO0 (0x0006),
CSKYV1_ISA_E1),
OP16 ("idly4",
OPCODE_INFO0 (0x0007),
CSKYV1_ISA_E1),
OP16 ("trap",
OPCODE_INFO1 (0x0008,
(0_1, IMM2b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mvtc",
OPCODE_INFO0 (0x000c),
CSKY_ISA_DSP),
OP16 ("cprc",
OPCODE_INFO0 (0x000d),
CSKY_ISA_CP),
OP16 ("cpseti",
OPCODE_INFO1 (0x0010,
(0_3, CPIDX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
OP16 ("mvc",
OPCODE_INFO1 (0x0020,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mvcv",
OPCODE_INFO1 (0x0030,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("ldq",
OPCODE_INFO2 (0x0040,
(NONE, REGr4_r7, OPRND_SHIFT_0_BIT),
(0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("stq",
OPCODE_INFO2 (0x0050,
(NONE, REGr4_r7, OPRND_SHIFT_0_BIT),
(0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("ldm",
OPCODE_INFO2 (0x0060,
(0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT),
(NONE, REGbsp, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("stm",
OPCODE_INFO2 (0x0070,
(0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT),
(NONE, REGbsp, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("dect",
OPCODE_INFO3 (0x0080,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0080,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("decf",
OPCODE_INFO3 (0x0090,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0090,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("inct",
OPCODE_INFO3 (0x00a0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x00a0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("incf",
OPCODE_INFO3 (0x00b0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x00b0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 2
OP16 ("jmp",
OPCODE_INFO1 (0x00c0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 0
OP16 ("jsr",
OPCODE_INFO1 (0x00d0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ff1",
OPCODE_INFO2 (0x00e0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x00e0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("brev",
OPCODE_INFO2 (0x00f0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x00f0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("xtrb3",
OPCODE_INFO2 (0x0100,
(NONE, REG_r1a, OPRND_SHIFT_0_BIT),
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0100,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("xtrb2",
OPCODE_INFO2 (0x0110,
(NONE, REG_r1a, OPRND_SHIFT_0_BIT),
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0110,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("xtrb1",
OPCODE_INFO2 (0x0120,
(NONE, REG_r1a, OPRND_SHIFT_0_BIT),
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0120,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("xtrb0",
OPCODE_INFO2 (0x0130,
(NONE, REG_r1a, OPRND_SHIFT_0_BIT),
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0130,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("zextb",
OPCODE_INFO2 (0x0140,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0140,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("sextb",
OPCODE_INFO2 (0x0150,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0150,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("zexth",
OPCODE_INFO2 (0x0160,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0160,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("sexth",
OPCODE_INFO2 (0x0170,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0170,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("declt",
OPCODE_INFO3 (0x0180,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x0180,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("tstnbz",
OPCODE_INFO1 (0x0190,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("decgt",
OPCODE_INFO3 (0x01a0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x01a0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("decne",
OPCODE_INFO3 (0x01b0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x01b0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("clrt",
OPCODE_INFO1 (0x01c0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("clrf",
OPCODE_INFO1 (0x01d0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("abs",
OPCODE_INFO2 (0x01e0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x01e0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("not",
OPCODE_INFO2 (0x01f0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x01f0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("movt",
OPCODE_INFO2 (0x0200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("mult",
OPCODE_INFO3 (0x0300,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x0300,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mac",
OPCODE_INFO2 (0x0400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC),
DOP16 ("subu",
OPCODE_INFO3 (0x0500,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x0500,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("sub",
OPCODE_INFO3 (0x0500,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x0500,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("addc",
OPCODE_INFO3 (0x0600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x0600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("subc",
OPCODE_INFO3 (0x0700,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x0700,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cprgr",
OPCODE_INFO2 (0x0800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, CPREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
OP16 ("movf",
OPCODE_INFO2 (0x0a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("lsr",
OPCODE_INFO3 (0x0b00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x0b00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cmphs",
OPCODE_INFO2 (0x0c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cmplt",
OPCODE_INFO2 (0x0d00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("tst",
OPCODE_INFO2 (0x0e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cmpne",
OPCODE_INFO2 (0x0f00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mfcr",
OPCODE_INFO2 (0x1000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, CTRLREG, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("psrclr",
OPCODE_INFO_LIST (0x11f0,
(0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("psrset",
OPCODE_INFO_LIST (0x11f8,
(0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mov",
OPCODE_INFO2 (0x1200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("bgenr",
OPCODE_INFO2 (0x1300,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("rsub",
OPCODE_INFO3 (0x1400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ixw",
OPCODE_INFO3 (0x1500,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1500,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("and",
OPCODE_INFO3 (0x1600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("xor",
OPCODE_INFO3 (0x1700,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1700,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mtcr",
OPCODE_INFO2 (0x1800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, CTRLREG, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("asr",
OPCODE_INFO3 (0x1a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("lsl",
OPCODE_INFO3 (0x1b00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1b00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("addu",
OPCODE_INFO3 (0x1c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("add",
OPCODE_INFO2 (0x1c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ixh",
OPCODE_INFO3 (0x1d00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1d00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("or",
OPCODE_INFO3 (0x1e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("andn",
OPCODE_INFO3 (0x1f00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x1f00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("addi",
OPCODE_INFO3 (0x2000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, OIMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x2000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, OIMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cmplti",
OPCODE_INFO2 (0x2200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, OIMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("subi",
OPCODE_INFO3 (0x2400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, OIMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x2400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, OIMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cpwgr",
OPCODE_INFO2 (0x2600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, CPREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
DOP16 ("rsubi",
OPCODE_INFO3 (0x2800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x2800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cmpnei",
OPCODE_INFO2 (0x2a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("bmaski",
OPCODE_INFO2 (0x2c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_BMASKI, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("divu",
OPCODE_INFO3 (0x2c10,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, REG_r1b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x2c10,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, REG_r1b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mflos",
OPCODE_INFO1 (0x2c20,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC_DSP),
OP16 ("mfhis",
OPCODE_INFO1 (0x2c30,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC_DSP),
OP16 ("mtlo",
OPCODE_INFO1 (0x2c40,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC_DSP),
OP16 ("mthi",
OPCODE_INFO1 (0x2c50,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC_DSP),
OP16 ("mflo",
OPCODE_INFO1 (0x2c60,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC_DSP),
OP16 ("mfhi",
OPCODE_INFO1 (0x2c70,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC_DSP),
DOP16 ("andi",
OPCODE_INFO3 (0x2e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x2e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("bclri",
OPCODE_INFO3 (0x3000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x3000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("bgeni",
OPCODE_INFO2 (0x3200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_7_31, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cpwir",
OPCODE_INFO1 (0x3200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
DOP16 ("divs",
OPCODE_INFO3 (0x3210,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, REG_r1b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x3210,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, REG_r1b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("cprsr",
OPCODE_INFO1 (0x3220,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
OP16 ("cpwsr",
OPCODE_INFO1 (0x3230,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
DOP16 ("bseti",
OPCODE_INFO3 (0x3400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x3400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("btsti",
OPCODE_INFO2 (0x3600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("rotli",
OPCODE_INFO3 (0x3800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x3800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("xsr",
OPCODE_INFO3 (0x3800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x3800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("asrc",
OPCODE_INFO3 (0x3a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x3a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("asri",
OPCODE_INFO3 (0x3a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x3a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("lslc",
OPCODE_INFO3 (0x3c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x3c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("lsli",
OPCODE_INFO3 (0x3c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x3c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("lsrc",
OPCODE_INFO3 (0x3e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(NONE, CONST1, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0x3e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("lsri",
OPCODE_INFO3 (0x3e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x3e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("ldex",
SOPCODE_INFO2 (0x4000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
CSKY_ISA_MP),
OP16 ("ldex.w",
SOPCODE_INFO2 (0x4000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
CSKY_ISA_MP),
OP16 ("ldwex",
SOPCODE_INFO2 (0x4000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
CSKY_ISA_MP),
OP16 ("stex",
SOPCODE_INFO2 (0x5000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
CSKY_ISA_MP),
OP16 ("stex.w",
SOPCODE_INFO2 (0x5000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
CSKY_ISA_MP),
OP16 ("stwex",
SOPCODE_INFO2 (0x5000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
CSKY_ISA_MP),
OP16 ("omflip0",
OPCODE_INFO2 (0x4000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC),
OP16 ("omflip1",
OPCODE_INFO2 (0x4100,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC),
OP16 ("omflip2",
OPCODE_INFO2 (0x4200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC),
OP16 ("omflip3",
OPCODE_INFO2 (0x4300,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MAC),
OP16 ("muls",
OPCODE_INFO2 (0x5000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulsa",
OPCODE_INFO2 (0x5100,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulss",
OPCODE_INFO2 (0x5200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulu",
OPCODE_INFO2 (0x5400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulua",
OPCODE_INFO2 (0x5500,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulus",
OPCODE_INFO2 (0x5600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("vmulsh",
OPCODE_INFO2 (0x5800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("vmulsha",
OPCODE_INFO2 (0x5900,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("vmulshs",
OPCODE_INFO2 (0x5a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("vmulsw",
OPCODE_INFO2 (0x5c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("vmulswa",
OPCODE_INFO2 (0x5d00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("vmulsws",
OPCODE_INFO2 (0x5e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("movi",
OPCODE_INFO2 (0x6000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_10, IMM7b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("mulsh",
OPCODE_INFO3 (0x6800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x6800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("mulsh.h",
OPCODE_INFO3 (0x6800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0x6800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("mulsha",
OPCODE_INFO2 (0x6900,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulshs",
OPCODE_INFO2 (0x6a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("cprcr",
OPCODE_INFO2 (0x6b00,
(0_2, GREG0_7, OPRND_SHIFT_0_BIT),
(3_7, CPCREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
OP16 ("mulsw",
OPCODE_INFO2 (0x6c00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulswa",
OPCODE_INFO2 (0x6d00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("mulsws",
OPCODE_INFO2 (0x6e00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP16 ("cpwcr",
OPCODE_INFO2 (0x6f00,
(0_2, GREG0_7, OPRND_SHIFT_0_BIT),
(3_7, CPCREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_CP),
#undef _RELOC16
#define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM8BY4
#undef _TRANSFER
#define _TRANSFER 1
OP16 ("jmpi",
OPCODE_INFO1 (0x7000,
(0_7, OFF8b, OPRND_SHIFT_2_BIT)),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 0
OP16 ("jsri",
OPCODE_INFO1 (0x7f00,
(0_7, OFF8b, OPRND_SHIFT_2_BIT)),
CSKYV1_ISA_E1),
OP16_WITH_WORK ("lrw",
OPCODE_INFO2 (0x7000,
(8_11, REGnsplr, OPRND_SHIFT_0_BIT),
(0_7, CONSTANT, OPRND_SHIFT_2_BIT)),
CSKYV1_ISA_E1,
v1_work_lrw),
#undef _RELOC16
#define _RELOC16 0
DOP16 ("ld.w",
SOPCODE_INFO2 (0x8000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_2_BIT))),
OPCODE_INFO2 (0x8000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ldw",
SOPCODE_INFO2 (0x8000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_2_BIT))),
OPCODE_INFO2 (0x8000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ld",
SOPCODE_INFO2 (0x8000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_2_BIT))),
OPCODE_INFO2 (0x8000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("st.w",
SOPCODE_INFO2 (0x9000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_2_BIT))),
OPCODE_INFO2 (0x9000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("stw",
SOPCODE_INFO2 (0x9000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_2_BIT))),
OPCODE_INFO2 (0x9000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("st",
SOPCODE_INFO2 (0x9000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_2_BIT))),
OPCODE_INFO2 (0x9000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ld.b",
SOPCODE_INFO2 (0xa000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
OPCODE_INFO2 (0xa000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ldb",
SOPCODE_INFO2 (0xa000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
OPCODE_INFO2 (0xa000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("st.b",
SOPCODE_INFO2 (0xb000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
OPCODE_INFO2 (0xb000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("stb",
SOPCODE_INFO2 (0xb000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_0_BIT))),
OPCODE_INFO2 (0xb000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ld.h",
SOPCODE_INFO2 (0xc000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_1_BIT))),
OPCODE_INFO2 (0xc000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("ldh",
SOPCODE_INFO2 (0xc000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_1_BIT))),
OPCODE_INFO2 (0xc000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("st.h",
SOPCODE_INFO2 (0xd000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_1_BIT))),
OPCODE_INFO2 (0xd000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
DOP16 ("sth",
SOPCODE_INFO2 (0xd000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_7, IMM_LDST, OPRND_SHIFT_1_BIT))),
OPCODE_INFO2 (0xd000,
(8_11, GREG0_15, OPRND_SHIFT_0_BIT),
(0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
#undef _RELOC16
#define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM11BY2
OP16 ("bt",
OPCODE_INFO1 (0xe000,
(0_10, OFF11b, OPRND_SHIFT_1_BIT)),
CSKYV1_ISA_E1),
OP16 ("bf",
OPCODE_INFO1 (0xe800,
(0_10, OFF11b, OPRND_SHIFT_1_BIT)),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 1
OP16 ("br",
OPCODE_INFO1 (0xf000,
(0_10, OFF11b, OPRND_SHIFT_1_BIT)),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 0
OP16 ("bsr",
OPCODE_INFO1 (0xf800,
(0_10, OFF11b, OPRND_SHIFT_1_BIT)),
CSKYV1_ISA_E1),
#undef _RELOC16
#define _RELOC16 0
#undef _RELAX
#define _RELAX 1
OP16 ("jbt",
OPCODE_INFO1 (0xe000,
(0_10, JBTF, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("jbf",
OPCODE_INFO1 (0xe800,
(0_10, JBTF, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 1
OP16 ("jbr",
OPCODE_INFO1 (0xf000,
(0_10, JBR, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 0
#undef _RELAX
#define _RELAX 0
OP16_WITH_WORK ("jbsr",
OPCODE_INFO1 (0xf800,
(0_10, JBSR, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1,
v1_work_jbsr),
/* The following are aliases for other instructions. */
/* rts -> jmp r15. */
#undef _TRANSFER
#define _TRANSFER 2
OP16 ("rts",
OPCODE_INFO0 (0x00CF),
CSKYV1_ISA_E1),
OP16 ("rte",
OPCODE_INFO0 (0x0002),
CSKYV1_ISA_E1),
OP16 ("rfe",
OPCODE_INFO0 (0x0002),
CSKYV1_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 0
/* cmphs r0,r0 */
OP16 ("setc",
OPCODE_INFO0 (0x0c00),
CSKYV1_ISA_E1),
/* cmpne r0,r0 */
OP16 ("clrc",
OPCODE_INFO0 (0x0f00),
CSKYV1_ISA_E1),
/* cmplti rd,1 */
OP16 ("tstle",
OPCODE_INFO1 (0x2200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* cmplei rd,X -> cmplti rd,X+1 */
OP16 ("cmplei",
OPCODE_INFO2 (0x2200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* rsubi rd,0 */
OP16 ("neg",
OPCODE_INFO1 (0x2800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* cmpnei rd,0. */
OP16 ("tstne",
OPCODE_INFO1 (0x2a00,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* btsti rx,31. */
OP16 ("tstlt",
OPCODE_INFO1 (0x37f0,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* bclri rx,log2(imm). */
OP16 ("mclri",
OPCODE_INFO2 (0x3000,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* bgeni rx,log2(imm). */
OP16 ("mgeni",
OPCODE_INFO2 (0x3200,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_7_31_POWER, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* bseti rx,log2(imm). */
OP16 ("mseti",
OPCODE_INFO2 (0x3400,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* btsti rx,log2(imm). */
OP16 ("mtsti",
OPCODE_INFO2 (0x3600,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("rori",
OPCODE_INFO2 (0x3800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
OP16 ("rotri",
OPCODE_INFO2 (0x3800,
(0_3, GREG0_15, OPRND_SHIFT_0_BIT),
(4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)),
CSKYV1_ISA_E1),
/* mov r0, r0. */
OP16 ("nop",
OPCODE_INFO0 (0x1200),
CSKYV1_ISA_E1),
/* Float instruction with work. */
OP16_WITH_WORK ("fabss",
OPCODE_INFO3 (0xffe04400,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnegs",
OPCODE_INFO3 (0xffe04c00,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fsqrts",
OPCODE_INFO3 (0xffe05400,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("frecips",
OPCODE_INFO3 (0xffe05c00,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fadds",
OPCODE_INFO4 (0xffe38000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fsubs",
OPCODE_INFO4 (0xffe48000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1, v1_work_fpu_fo),
OP16_WITH_WORK ("fmacs",
OPCODE_INFO4 (0xffe58000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmscs",
OPCODE_INFO4 (0xffe68000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmuls",
OPCODE_INFO4 (0xffe78000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fdivs",
OPCODE_INFO4 (0xffe88000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmacs",
OPCODE_INFO4 (0xffe98000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmscs",
OPCODE_INFO4 (0xffea8000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmuls",
OPCODE_INFO4 (0xffeb8000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(10_14, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fabsd",
OPCODE_INFO3 (0xffe04000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnegd",
OPCODE_INFO3 (0xffe04800,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fsqrtd",
OPCODE_INFO3 (0xffe05000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("frecipd",
OPCODE_INFO3 (0xffe05800,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("faddd",
OPCODE_INFO4 (0xffe30000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fsubd",
OPCODE_INFO4 (0xffe40000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmacd",
OPCODE_INFO4 (0xffe50000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmscd",
OPCODE_INFO4 (0xffe60000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmuld",
OPCODE_INFO4 (0xffe70000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fdivd",
OPCODE_INFO4 (0xffe80000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmacd",
OPCODE_INFO4 (0xffe90000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmscd",
OPCODE_INFO4 (0xffea0000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmuld",
OPCODE_INFO4 (0xffeb0000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fabsm",
OPCODE_INFO3 (0xffe06000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnegm",
OPCODE_INFO3 (0xffe06400,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("faddm",
OPCODE_INFO4 (0xffec0000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fsubm",
OPCODE_INFO4 (0xffec8000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmacm",
OPCODE_INFO4 (0xffed8000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmscm",
OPCODE_INFO4 (0xffee0000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmulm",
OPCODE_INFO4 (0xffed0000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmacm",
OPCODE_INFO4 (0xffee8000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmscm",
OPCODE_INFO4 (0xffef0000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fnmulm",
OPCODE_INFO4 (0xffef8000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(10_14, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fcmphsd",
OPCODE_INFO3 (0xffe00800,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpltd",
OPCODE_INFO3 (0xffe00c00,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpned",
OPCODE_INFO3 (0xffe01000,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpuod",
OPCODE_INFO3 (0xffe01400,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmphss",
OPCODE_INFO3 (0xffe01800,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(5_9, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmplts",
OPCODE_INFO3 (0xffe01c00,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(5_9, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpnes",
OPCODE_INFO3 (0xffe02000,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(5_9, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpuos",
OPCODE_INFO3 (0xffe02400,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(5_9, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpzhsd",
OPCODE_INFO2 (0xffe00400,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpzltd",
OPCODE_INFO2 (0xffe00480,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpzned",
OPCODE_INFO2 (0xffe00500,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpzuod",
OPCODE_INFO2 (0xffe00580,
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpzhss",
OPCODE_INFO2 (0xffe00600,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpzlts",
OPCODE_INFO2 (0xffe00680,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpznes",
OPCODE_INFO2 (0xffe00700,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fcmpzuos",
OPCODE_INFO2 (0xffe00780,
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo_fc),
OP16_WITH_WORK ("fstod",
OPCODE_INFO3 (0xffe02800,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fdtos",
OPCODE_INFO3 (0xffe02c00,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fsitos",
OPCODE_INFO3 (0xffe03400,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fsitod",
OPCODE_INFO3 (0xffe03000,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fuitos",
OPCODE_INFO3 (0xffe03c00,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fuitod",
OPCODE_INFO3 (0xffe03800,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fstosi",
OPCODE_INFO4 (0xffe10000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(13_17, RM, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fdtosi",
OPCODE_INFO4 (0xffe08000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(13_17, RM, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fstoui",
OPCODE_INFO4 (0xffe20000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(13_17, RM, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fdtoui",
OPCODE_INFO4 (0xffe18000,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FEREG, OPRND_SHIFT_0_BIT),
(13_17, RM, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmovd",
OPCODE_INFO3 (0xffe06800,
(5_9, FEREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmovs",
OPCODE_INFO3 (0xffe06c00,
(5_9, FREG, OPRND_SHIFT_0_BIT),
(0_4, FREG, OPRND_SHIFT_0_BIT),
(NONE, GREG0_15, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_fo),
OP16_WITH_WORK ("fmts",
OPCODE_INFO2 (0x00000000,
(NONE, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, FREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_write),
OP16_WITH_WORK ("fmfs",
OPCODE_INFO2 (0x00000000,
(NONE, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, FREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_read),
OP16_WITH_WORK ("fmtd",
OPCODE_INFO2 (0x00000000,
(NONE, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, FEREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_writed),
OP16_WITH_WORK ("fmfd",
OPCODE_INFO2 (0x00000000,
(NONE, GREG0_15, OPRND_SHIFT_0_BIT),
(NONE, FEREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_E1,
v1_work_fpu_readd),
{NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL}
};
#undef _TRANSFER
#undef _RELOC16
#undef _RELOC32
#undef _RELAX
/* C-SKY v2 opcodes. */
const struct csky_opcode csky_v2_opcodes[] =
{
#define _TRANSFER 0
#define _RELOC16 0
#define _RELOC32 0
#define _RELAX 0
OP16 ("bkpt",
OPCODE_INFO0 (0x0000),
CSKYV2_ISA_E1),
OP16_WITH_WORK ("nie",
OPCODE_INFO0 (0x1460),
CSKYV2_ISA_E1,
v2_work_istack),
OP16_WITH_WORK ("nir",
OPCODE_INFO0 (0x1461),
CSKYV2_ISA_E1,
v2_work_istack),
OP16_WITH_WORK ("ipush",
OPCODE_INFO0 (0x1462),
CSKYV2_ISA_E1,
v2_work_istack),
OP16_WITH_WORK ("ipop",
OPCODE_INFO0 (0x1463),
CSKYV2_ISA_E1,
v2_work_istack),
OP16 ("bpop.h",
OPCODE_INFO1 (0x14a0,
(2_4, GREG0_7, OPRND_SHIFT_0_BIT)),
CSKY_ISA_JAVA),
OP16 ("bpop.w",
OPCODE_INFO1 (0x14a2,
(2_4, GREG0_7, OPRND_SHIFT_0_BIT)),
CSKY_ISA_JAVA),
OP16 ("bpush.h",
OPCODE_INFO1 (0x14e0,
(2_4, GREG0_7, OPRND_SHIFT_0_BIT)),
CSKY_ISA_JAVA),
OP16 ("bpush.w",
OPCODE_INFO1 (0x14e2,
(2_4, GREG0_7, OPRND_SHIFT_0_BIT)),
CSKY_ISA_JAVA),
OP32 ("bmset",
OPCODE_INFO0 (0xc0001020),
CSKY_ISA_JAVA),
OP32 ("bmclr",
OPCODE_INFO0 (0xc0001420),
CSKY_ISA_JAVA),
OP32 ("sce",
OPCODE_INFO1 (0xc0001820,
(21_24, IMM4b, OPRND_SHIFT_0_BIT)),
CSKY_ISA_MP),
OP32 ("trap",
OPCODE_INFO1 (0xc0002020,
(10_11, IMM2b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_E1),
/* Secure/nsecure world switch. */
OP32 ("wsc",
OPCODE_INFO0 (0xc0003c20),
CSKY_ISA_TRUST),
OP32 ("mtcr",
OPCODE_INFO2 (0xc0006420,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(0_4or21_25, CTRLREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_E1),
OP32 ("mfcr",
OPCODE_INFO2 (0xc0006020,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20or21_25, CTRLREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_E1),
#undef _TRANSFER
#define _TRANSFER 2
OP32 ("rte",
OPCODE_INFO0 (0xc0004020),
CSKYV2_ISA_E1),
OP32 ("rfi",
OPCODE_INFO0 (0xc0004420),
CSKYV2_ISA_2E3),
#undef _TRANSFER
#define _TRANSFER 0
OP32 ("stop",
OPCODE_INFO0 (0xc0004820),
CSKYV2_ISA_E1),
OP32 ("wait",
OPCODE_INFO0 (0xc0004c20),
CSKYV2_ISA_E1),
OP32 ("doze",
OPCODE_INFO0 (0xc0005020),
CSKYV2_ISA_E1),
OP32 ("we",
OPCODE_INFO0 (0xc0005420),
CSKY_ISA_MP_1E2),
OP32 ("se",
OPCODE_INFO0 (0xc0005820),
CSKY_ISA_MP_1E2),
OP32 ("psrclr",
OPCODE_INFO_LIST (0xc0007020,
(21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_E1),
OP32 ("psrset",
OPCODE_INFO_LIST (0xc0007420,
(21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_E1),
DOP32 ("abs",
OPCODE_INFO2 (0xc4000200,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0xc4000200,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
OP32 ("mvc",
OPCODE_INFO1 (0xc4000500,
(0_4, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("incf",
OPCODE_INFO3 (0xc4000c20,
(21_25, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("movf",
OPCODE_INFO2 (0xc4000c20,
(21_25, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("inct",
OPCODE_INFO3 (0xc4000c40,
(21_25, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("movt",
OPCODE_INFO2 (0xc4000c40,
(21_25, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("decf",
OPCODE_INFO3 (0xc4000c80,
(21_25, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("dect",
OPCODE_INFO3 (0xc4000d00,
(21_25, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("decgt",
OPCODE_INFO3 (0xc4001020,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
OP32 ("declt",
OPCODE_INFO3 (0xc4001040,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
OP32 ("decne",
OPCODE_INFO3 (0xc4001080,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
OP32 ("clrf",
OPCODE_INFO1 (0xc4002c20,
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
OP32 ("clrt",
OPCODE_INFO1 (0xc4002c40,
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
DOP32 ("rotli",
OPCODE_INFO3 (0xc4004900,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, IMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO2 (0xc4004900,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT),
(21_25, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("lslc",
OPCODE_INFO3 (0xc4004c20,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, OIMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("lsrc",
OPCODE_INFO3 (0xc4004c40,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, OIMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
DOP32 ("asrc",
OPCODE_INFO3 (0xc4004c80,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, OIMM5b, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0xc4004c80,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("xsr",
OPCODE_INFO3 (0xc4004d00,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, OIMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("bgenr",
OPCODE_INFO2 (0xc4005040,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
DOP32 ("brev",
OPCODE_INFO2 (0xc4006200,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0xc4006200,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
OP32 ("xtrb0",
OPCODE_INFO2 (0xc4007020,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("xtrb1",
OPCODE_INFO2 (0xc4007040,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("xtrb2",
OPCODE_INFO2 (0xc4007080,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("xtrb3",
OPCODE_INFO2 (0xc4007100,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("ff0",
OPCODE_INFO2 (0xc4007c20,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
DOP32 ("ff1",
OPCODE_INFO2 (0xc4007c40,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
OPCODE_INFO1 (0xc4007c40,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
OP32 ("mulu",
OPCODE_INFO2 (0xc4008820,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulua",
OPCODE_INFO2 (0xc4008840,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulus",
OPCODE_INFO2 (0xc4008880,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("muls",
OPCODE_INFO2 (0xc4008c20,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulsa",
OPCODE_INFO2 (0xc4008c40,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulss",
OPCODE_INFO2 (0xc4008c80,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulsha",
OPCODE_INFO2 (0xc4009040,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulshs",
OPCODE_INFO2 (0xc4009080,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulswa",
OPCODE_INFO2 (0xc4009440,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulsws",
OPCODE_INFO2 (0xc4009500,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mfhis",
OPCODE_INFO1 (0xc4009820,
(0_4, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mflos",
OPCODE_INFO1 (0xc4009880,
(0_4, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mvtc",
OPCODE_INFO0 (0xc4009a00),
CSKY_ISA_DSPE60),
OP32 ("mfhi",
OPCODE_INFO1 (0xc4009c20,
(0_4, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mthi",
OPCODE_INFO1 (0xc4009c40,
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mflo",
OPCODE_INFO1 (0xc4009c80,
(0_4, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mtlo",
OPCODE_INFO1 (0xc4009d00,
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("vmulsh",
OPCODE_INFO2 (0xc400b020,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP_1E2),