)]}'
{
  "commit": "b8b60e2d0cb0ab1f235f082dbb8a4e8bc43aadf6",
  "tree": "5f3fc4f0f9f924dbe125b946dcfe81374a015209",
  "parents": [
    "a3f1e7c56a60573562e8578ae8b675ec1f4448e7"
  ],
  "author": {
    "name": "Jens Remus",
    "email": "jremus@linux.ibm.com",
    "time": "Thu Sep 12 15:06:06 2024 +0200"
  },
  "committer": {
    "name": "Jens Remus",
    "email": "jremus@linux.ibm.com",
    "time": "Thu Sep 12 15:06:06 2024 +0200"
  },
  "message": "s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints\n\nThis leverages commit (\"s390: Simplify (dis)assembly of insn operands\nwith const bits\") to relax the operand constraints of the immediate\noperand that contains the constant Z- or T-bit of the following extended\nmnemonics:\nrisbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt\n\nPreviously those instructions were the only ones where the assembler\non s390 restricted the specification of the subject I3/I4 operand values\nexactly according to their specification to an unsigned 6- or 5-bit\nunsigned integer. For any other instructions the assembler allows to\nspecify any operand value allowed by the instruction format, regardless\nof whether the instruction specification is more restrictive.\n\nAllow to specify the subject I3/I4 operand as unsigned 8-bit integer\nwith the constant operand bits being ORed during assembly.\nRelax the instructions subject significant operand bit masks to only\nconsider the Z/T-bit as significant, so that the instructions get\ndisassembled as their *z or *t flavor regardless of whether any reserved\nbits are set in addition to the Z/T-bit.\nAdapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set\nthe T-bit in operand I3, as they otherwise get disassembled as their\nrnsbgt, rosbgt, and rxsbgt counterpart.\n\nThis aligns GNU Assembler to LLVM Assembler.\n\nopcodes/\n\t* s390-opc.c (U6_18, U5_27, U6_26): Remove.\n\t(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define\n\tas INSTR_RIE_RRUUU while retaining insn fmt mask.\n\t(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only\n\tZ/T-bit of I3/I4 operand as significant.\n\ngas/testsuite/\n\t* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.\n\nReported-by: Dominik Steenken \u003cdost@de.ibm.com\u003e\nSuggested-by: Ulrich Weigand \u003culrich.weigand@de.ibm.com\u003e\nSigned-off-by: Jens Remus \u003cjremus@linux.ibm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4a051533f93af56989ae1d0cb6dd2dd1f75ae38b",
      "old_mode": 33188,
      "old_path": "gas/testsuite/gas/s390/zarch-z10.d",
      "new_id": "beb057878d6647fa94635cc20fc6116cf390f21f",
      "new_mode": 33188,
      "new_path": "gas/testsuite/gas/s390/zarch-z10.d"
    },
    {
      "type": "modify",
      "old_id": "45bb89447938214c5fd8e1be5072d47ab2079095",
      "old_mode": 33188,
      "old_path": "gas/testsuite/gas/s390/zarch-z10.s",
      "new_id": "a6245888c4c3da3484167059e0b15d55aa778de1",
      "new_mode": 33188,
      "new_path": "gas/testsuite/gas/s390/zarch-z10.s"
    },
    {
      "type": "modify",
      "old_id": "987004d7b0708ba7e1546b3f0ae73662490d2ed1",
      "old_mode": 33188,
      "old_path": "opcodes/s390-opc.c",
      "new_id": "fe0299aa4e5d10b9a4a0f7f02105e2ff4a243972",
      "new_mode": 33188,
      "new_path": "opcodes/s390-opc.c"
    }
  ]
}