)]}'
{
  "commit": "b9593cb70533f28d276ab8d582dfe622aa4591d5",
  "tree": "e3222ab019a57858835bc10e4aa07d5fcf3d0573",
  "parents": [
    "06c00d5feaf78869b42c28f9b5519c922a6dc765"
  ],
  "author": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Sun Sep 04 07:45:06 2022 +0000"
  },
  "committer": {
    "name": "Andrew Burgess",
    "email": "aburgess@redhat.com",
    "time": "Mon Sep 05 09:42:06 2022 +0100"
  },
  "message": "sim/riscv: Complete tidying up with SBREAK\n\nThis commit removes SBREAK-related references on the simulator as it\u0027s\nrenamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).\n\nsim/ChangeLog:\n\n\t* riscv/sim-main.c (execute_i): Use \"ebreak\" instead of \"sbreak\".\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "62f475671c9d3b286367a358b82ed14d44ca6522",
      "old_mode": 33188,
      "old_path": "sim/riscv/sim-main.c",
      "new_id": "30d2f1e1c9a9db2857f36c49ebcea32d2883082e",
      "new_mode": 33188,
      "new_path": "sim/riscv/sim-main.c"
    }
  ]
}