)]}'
{
  "commit": "b9915cbc7d3ac2b9cd136248defbf9538b9a9bcf",
  "tree": "f99be238a8f95c1690e68193c96df0028da708ae",
  "parents": [
    "ce504911e5c4068a3498eebde4064b24382c7598"
  ],
  "author": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Mon Feb 17 08:56:18 2020 +0100"
  },
  "committer": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Mon Feb 17 08:56:18 2020 +0100"
  },
  "message": "x86/Intel: improve diagnostics for ambiguous VCVT* operands\n\nConversions which shrink element size and which have a memory source\ncan\u0027t be disambiguated between their 128- and 256-bit variants by\nlooking at the register operand. \"operand size mismatch\", however, is a\npretty misleading diagnostic. Generalize the logic introduced for\nVFPCLASSP{S,D} such that, with suitable similar adjustments to the\nrespective templates, it\u0027ll cover these cases too.\n\nFor VCVTNEPS2BF16 also fold the two previously separate AVX512VL\ntemplates to achieve the intended effect. This is then also accompanied\nby a respective addition to the inval-avx512f testcase.\n",
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