Remove annoying spaces from objcopy.exp
diff --git a/binutils/testsuite/binutils-all/objcopy.exp b/binutils/testsuite/binutils-all/objcopy.exp
index ff93fea..cf94570 100644
--- a/binutils/testsuite/binutils-all/objcopy.exp
+++ b/binutils/testsuite/binutils-all/objcopy.exp
@@ -180,7 +180,7 @@
untested "verilog width-4 and width-8 tests"
return
}
-
+
foreach width {4 8} {
set got [binutils_run $OBJCOPY "-O verilog --verilog-data-width $width $binfile $verilog-$width.hex"]
if ![string equal "" $got] then {
@@ -194,7 +194,7 @@
}
}
- # Test generating endian correct output.
+ # Test generating endian correct output.
set testname "objcopy (verilog output endian-ness == input endian-ness)"
set got [binutils_run $OBJCOPY "-O verilog --verilog-data-width 4 $binfile $verilog-I4.hex"]
if ![string equal "" $got] then {
@@ -202,9 +202,9 @@
}
send_log "regexp_diff $verilog-I4.hex $srcdir/$subdir/verilog-I4.hex\n"
if {! [regexp_diff "$verilog-I4.hex" "$srcdir/$subdir/verilog-I4.hex"]} {
- pass $testname
+ pass $testname
} else {
- fail $testname
+ fail $testname
}
}
