)]}'
{
  "commit": "c6422d7be70f14bf7140085f2fc7a592737f5df5",
  "tree": "689a30410844160256c47c3ef26542026ff39fa8",
  "parents": [
    "029b1ee8d8805ba8cbc4481c107c8e5f32b48eab"
  ],
  "author": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Wed Aug 31 01:46:08 2022 +0000"
  },
  "committer": {
    "name": "Andrew Burgess",
    "email": "aburgess@redhat.com",
    "time": "Tue Oct 11 12:38:36 2022 +0100"
  },
  "message": "sim/riscv: fix multiply instructions on simulator\n\nAfter this commit:\n\n  commit 0938b032daa52129b4215d8e0eedb6c9804f5280\n  Date:   Wed Feb 2 10:06:15 2022 +0900\n\n      RISC-V: Add \u0027Zmmul\u0027 extension in assembler.\n\nsome instructions in the RISC-V simulator stopped working as a new\ninstruction class \u0027INSN_CLASS_ZMMUL\u0027 was added, and some existing\ninstructions were moved into this class.\n\nThe simulator doesn\u0027t currently handle this instruction class, and so\nthe instructions will now cause an illegal instruction trap.\n\nThis commit adds support for INSN_CLASS_ZMMUL, and adds a test that\nensures the affected instructions can be executed by the simulator.\n\nReviewed-by: Palmer Dabbelt \u003cpalmer@rivosinc.com\u003e\nReviewed-by: Andrew Burgess \u003caburgess@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "30d2f1e1c9a9db2857f36c49ebcea32d2883082e",
      "old_mode": 33188,
      "old_path": "sim/riscv/sim-main.c",
      "new_id": "0156f791d4b91fff57c4697d865ba91ae7c95a3a",
      "new_mode": 33188,
      "new_path": "sim/riscv/sim-main.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b80bd140e76c6aad37be1d4f6679dc52340e2020",
      "new_mode": 33188,
      "new_path": "sim/testsuite/riscv/m-ext.s"
    }
  ]
}