tree 689a30410844160256c47c3ef26542026ff39fa8
parent 029b1ee8d8805ba8cbc4481c107c8e5f32b48eab
author Tsukasa OI <research_trasio@irq.a4lg.com> 1661910368 +0000
committer Andrew Burgess <aburgess@redhat.com> 1665488316 +0100

sim/riscv: fix multiply instructions on simulator

After this commit:

  commit 0938b032daa52129b4215d8e0eedb6c9804f5280
  Date:   Wed Feb 2 10:06:15 2022 +0900

      RISC-V: Add 'Zmmul' extension in assembler.

some instructions in the RISC-V simulator stopped working as a new
instruction class 'INSN_CLASS_ZMMUL' was added, and some existing
instructions were moved into this class.

The simulator doesn't currently handle this instruction class, and so
the instructions will now cause an illegal instruction trap.

This commit adds support for INSN_CLASS_ZMMUL, and adds a test that
ensures the affected instructions can be executed by the simulator.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Andrew Burgess <aburgess@redhat.com>