)]}'
{
  "commit": "c8c6ef3807554a17d4518e45f91c53d17a71c083",
  "tree": "ad91bd4587ccf247736aae694accac89b6b10c06",
  "parents": [
    "ab230d13fc81986c4a74688e35510a8985dff422"
  ],
  "author": {
    "name": "Mike Frysinger",
    "email": "vapier@gentoo.org",
    "time": "Sun Nov 28 00:23:16 2021 -0500"
  },
  "committer": {
    "name": "Mike Frysinger",
    "email": "vapier@gentoo.org",
    "time": "Sun Nov 28 13:23:58 2021 -0500"
  },
  "message": "sim: riscv: switch to new target-newlib-syscall\n\nUse the new target-newlib-syscall module.  This is needed to merge all\nthe architectures into a single build, and riscv has a custom syscall\ntable for its newlib/libgloss port.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "17cb288eba3d3a7df5f3aca65bc4c5ea449540e3",
      "old_mode": 33188,
      "old_path": "sim/riscv/Makefile.in",
      "new_id": "b967654d7875dd1abf34aa48588a102b45d0fd6c",
      "new_mode": 33188,
      "new_path": "sim/riscv/Makefile.in"
    },
    {
      "type": "modify",
      "old_id": "efa4b5669cb3fc82dd7a9bd922cfd497f8517bef",
      "old_mode": 33188,
      "old_path": "sim/riscv/interp.c",
      "new_id": "13fe6c7cae0d09732fbb8a29001fdc69c83703f0",
      "new_mode": 33188,
      "new_path": "sim/riscv/interp.c"
    }
  ]
}