)]}'
{
  "commit": "c8cb37347fde3ae12c943c2133a1043eece4c127",
  "tree": "0605dc42c2c8534960374271cd486567a2ca8a0d",
  "parents": [
    "4ced24d1907a8ce28868cc3fe403d769197352be"
  ],
  "author": {
    "name": "Christoph Müllner",
    "email": "christoph.muellner@vrull.eu",
    "time": "Fri Jun 30 22:43:33 2023 +0200"
  },
  "committer": {
    "name": "Christoph Müllner",
    "email": "christoph.muellner@vrull.eu",
    "time": "Sat Jul 01 07:14:45 2023 +0200"
  },
  "message": "RISC-V: Add support for the Zvbb ISA extension\n\nZvbb is part of the vector crypto extensions.\n\nThis extension adds the following instructions:\n- vandn.[vv,vx]\n- vbrev.v\n- vbrev8.v\n- vrev8.v\n- vclz.v\n- vctz.v\n- vcpop.v\n- vrol.[vv,vx]\n- vror.[vv,vx,vi]\n- vwsll.[vv,vx,vi]\n\nbfd/ChangeLog:\n\n\t* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction\n\tclass support for Zvbb.\n\t(riscv_multi_subset_supports_ext): Likewise.\n\ngas/ChangeLog:\n\n\t* config/tc-riscv.c (validate_riscv_insn): Add \u0027l\u0027 as new format\n\tstring directive.\n\t(riscv_ip): Likewise.\n\t* testsuite/gas/riscv/zvbb.d: New test.\n\t* testsuite/gas/riscv/zvbb.s: New test.\n\ninclude/ChangeLog:\n\n\t* opcode/riscv-opc.h (MATCH_VANDN_VV): New.\n\t(MASK_VANDN_VV): New.\n\t(MATCH_VANDN_VX): New.\n\t(MASK_VANDN_VX): New.\n\t(MATCH_VBREV8_V): New.\n\t(MASK_VBREV8_V): New.\n\t(MATCH_VBREV_V): New.\n\t(MASK_VBREV_V): New.\n\t(MATCH_VCLZ_V): New.\n\t(MASK_VCLZ_V): New.\n\t(MATCH_VCPOP_V): New.\n\t(MASK_VCPOP_V): New.\n\t(MATCH_VCTZ_V): New.\n\t(MASK_VCTZ_V): New.\n\t(MATCH_VREV8_V): New.\n\t(MASK_VREV8_V): New.\n\t(MATCH_VROL_VV): New.\n\t(MASK_VROL_VV): New.\n\t(MATCH_VROL_VX): New.\n\t(MASK_VROL_VX): New.\n\t(MATCH_VROR_VI): New.\n\t(MASK_VROR_VI): New.\n\t(MATCH_VROR_VV): New.\n\t(MASK_VROR_VV): New.\n\t(MATCH_VROR_VX): New.\n\t(MASK_VROR_VX): New.\n\t(MATCH_VWSLL_VI): New.\n\t(MASK_VWSLL_VI): New.\n\t(MATCH_VWSLL_VV): New.\n\t(MASK_VWSLL_VV): New.\n\t(MATCH_VWSLL_VX): New.\n\t(MASK_VWSLL_VX): New.\n\t(DECLARE_INSN): New.\n\t* opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New.\n\t(ENCODE_RVV_VI_UIMM6): New.\n\t(enum riscv_insn_class): Add instruction class for Zvbb.\n\nopcodes/ChangeLog:\n\n\t* riscv-dis.c (print_insn_args): Add \u0027l\u0027 as new format string\n\tdirective.\n\t* riscv-opc.c: Add Zvbb instructions.\n\nSigned-off-by: Nathan Huckleberry \u003cnhuck@google.com\u003e\nSigned-off-by: Christoph Müllner \u003cchristoph.muellner@vrull.eu\u003e\n",
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