)]}'
{
  "commit": "c8ea5e409b02cf7fa848e44af74b2e8246ad03f1",
  "tree": "f6e56dda5d6f27de6c200d19ee1f105bef162ba0",
  "parents": [
    "40849d84cbcc7647edf90ab8078d873fab15ffb8"
  ],
  "author": {
    "name": "Xiao Zeng",
    "email": "zengxiao@eswincomputing.com",
    "time": "Tue Dec 06 14:59:43 2022 +0800"
  },
  "committer": {
    "name": "Andrew Burgess",
    "email": "aburgess@redhat.com",
    "time": "Tue Dec 06 10:18:19 2022 +0000"
  },
  "message": "gdb/riscv: correct dwarf to gdb register number mapping\n\nAccording to the riscv psabi, the mapping relationship between the\nDWARF registers and the machine registers is as follows:\n\n  DWARF Number | Register Name | Description\n  0 - 31       | x0 - x31      | Integer Registers\n  32 - 63      | f0 - f31      | Floating-point Registers\n\nThis is not modelled quite right in riscv_dwarf_reg_to_regnum, the\nDWARF register numbers 31 and 63 are not handled correctly due to a\nuse of \u0027\u003c\u0027 instead of \u0027\u003c\u003d\u0027.  This commit fixes this issue.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0a050b272ffff6d579dae2ee7701671f85211ee4",
      "old_mode": 33188,
      "old_path": "gdb/riscv-tdep.c",
      "new_id": "a298623b44921947135f0ff6882d0d01de3d4039",
      "new_mode": 33188,
      "new_path": "gdb/riscv-tdep.c"
    }
  ]
}