)]}'
{
  "commit": "ca2590d7804b4ea563eec6f1127ed17a00c30315",
  "tree": "850d78027e02d5d5e9cf5eb4fda22c6f9ade5cfd",
  "parents": [
    "47649afc965a611478f3dc42c43772ca8f182df4"
  ],
  "author": {
    "name": "Jiawei",
    "email": "jiawei@iscas.ac.cn",
    "time": "Tue Aug 20 10:10:21 2024 +0800"
  },
  "committer": {
    "name": "Nelson Chu",
    "email": "nelson@rivosinc.com",
    "time": "Tue Aug 27 10:25:49 2024 +0800"
  },
  "message": "RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.\n\nThis patch supports Zcmp instruction \u0027cm.mva01s\u0027 and \u0027cm.mvsa01\u0027.\nAll disassemble instructions use the sreg format.\n\nCo-Authored by: Charlie Keaney \u003ccharlie.keaney@embecosm.com\u003e\nCo-Authored by: Mary Bennett \u003cmary.bennett@embecosm.com\u003e\nCo-Authored by: Nandni Jamnadas \u003cnandni.jamnadas@embecosm.com\u003e\nCo-Authored by: Sinan Lin \u003csinan.lin@linux.alibaba.com\u003e\nCo-Authored by: Simon Cook \u003csimon.cook@embecosm.com\u003e\nCo-Authored by: Shihua Liao \u003cshihua@iscas.ac.cn\u003e\nCo-Authored by: Yulong Shi \u003cyulong@iscas.ac.cn\u003e\n\ngas/ChangeLog:\n\tPR 32036\n\t* NEWS: Updated.\n        * config/tc-riscv.c (validate_riscv_insn): New operators.\n        (riscv_ip): Ditto.\n        * testsuite/gas/riscv/zcmp-mv.d: New test.\n        * testsuite/gas/riscv/zcmp-mv.s: New test.\n\ninclude/ChangeLog:\n\tPR 32036\n        * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode.\n        (MASK_CM_MVA01S): New mask.\n        (MATCH_CM_MVSA01): New opcode.\n        (MASK_CM_MVSA01): New mask.\n        (DECLARE_INSN): New declarations.\n        * opcode/riscv.h (OP_MASK_SREG1): New mask.\n        (OP_SH_SREG1): New operand code.\n        (OP_MASK_SREG2): New mask.\n        (OP_SH_SREG2): New operand code.\n        (X_A0): New reg number.\n        (X_A1): Ditto.\n        (X_S7): Ditto.\n        (RISCV_SREG_0_7): New macro function.\n\nopcodes/ChangeLog:\n\tPR 32036\n        * riscv-dis.c (riscv_zcmp_get_sregno): New function.\n        (print_insn_args): New operators.\n        * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.\n",
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