# Intel(r) Wireless MMX(tm) technology testcase for WROR
# mach: xscale
# as: -mcpu=xscale+iwmmxt

	.include "testutils.inc"

	start

	.global wror
wror:
	# Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.

	mvi_h_gr   r1, 3
	mcr        p15, 0, r1, cr15, cr1, 0

	# Test Halfword wide rotate right by register
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0x00000000
	mvi_h_gr   r4, 0
	mvi_h_gr   r5, 0

	tmcrr	   wr0, r0, r1
	tmcrr	   wr1, r2, r3
	tmcrr	   wr2, r4, r5

	wrorh	   wr2, wr0, wr1
	
	tmrrc	   r0, r1, wr0
	tmrrc	   r2, r3, wr1
	tmrrc	   r4, r5, wr2
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x00000000
	test_h_gr  r4, 0x091a2b3c
	test_h_gr  r5, 0x4d5e6f78
	
	# Test Halfword wide rotate right by CG register
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0
	mvi_h_gr   r4, 0

	tmcrr	   wr0, r0, r1
	tmcr	   wcgr0, r2
	tmcrr	   wr1, r2, r3

	wrorhg	   wr1, wr0, wcgr0
	
	tmrrc	   r0, r1, wr0
	tmrc	   r2, wcgr0
	tmrrc	   r3, r4, wr2
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x091a2b3c
	test_h_gr  r4, 0x4d5e6f78
	
	# Test Word wide rotate right by register
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0x00000000
	mvi_h_gr   r4, 0
	mvi_h_gr   r5, 0

	tmcrr	   wr0, r0, r1
	tmcrr	   wr1, r2, r3
	tmcrr	   wr2, r4, r5

	wrorw	   wr2, wr0, wr1
	
	tmrrc	   r0, r1, wr0
	tmrrc	   r2, r3, wr1
	tmrrc	   r4, r5, wr2
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x00000000
	test_h_gr  r4, 0x2b3c091a
	test_h_gr  r5, 0x6f784d5e
	
	# Test Word wide rotate right by CG register
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0
	mvi_h_gr   r4, 0

	tmcrr	   wr0, r0, r1
	tmcr	   wcgr0, r2
	tmcrr	   wr1, r2, r3

	wrorwg	   wr1, wr0, wcgr0
	
	tmrrc	   r0, r1, wr0
	tmrc	   r2, wcgr0
	tmrrc	   r3, r4, wr2
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x2b3c091a
	test_h_gr  r4, 0x6f784d5e
	
	# Test Double Word wide rotate right by register
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0x00000000
	mvi_h_gr   r4, 0
	mvi_h_gr   r5, 0

	tmcrr	   wr0, r0, r1
	tmcrr	   wr1, r2, r3
	tmcrr	   wr2, r4, r5

	wrord	   wr2, wr0, wr1
	
	tmrrc	   r0, r1, wr0
	tmrrc	   r2, r3, wr1
	tmrrc	   r4, r5, wr2
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x00000000
	test_h_gr  r4, 0x6f78091a
	test_h_gr  r5, 0x2b3c4d5e
	
	# Test Double Word wide rotate right by CG register
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0
	mvi_h_gr   r4, 0

	tmcrr	   wr0, r0, r1
	tmcr	   wcgr0, r2
	tmcrr	   wr1, r2, r3

	wrordg	   wr1, wr0, wcgr0
	
	tmrrc	   r0, r1, wr0
	tmrc	   r2, wcgr0
	tmrrc	   r3, r4, wr2
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x6f78091a
	test_h_gr  r4, 0x2b3c4d5e
	
	pass