/* CPU data for frv.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "frv-desc.h"
#include "frv-opc.h"
#include "opintl.h"
#include "libiberty.h"

/* Attributes.  */

static const CGEN_ATTR_ENTRY bool_attr[] =
{
  { "#f", 0 },
  { "#t", 1 },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY MACH_attr[] =
{
  { "base", MACH_BASE },
  { "frv", MACH_FRV },
  { "fr500", MACH_FR500 },
  { "fr400", MACH_FR400 },
  { "tomcat", MACH_TOMCAT },
  { "simple", MACH_SIMPLE },
  { "max", MACH_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY ISA_attr[] =
{
  { "frv", ISA_FRV },
  { "max", ISA_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY UNIT_attr[] =
{
  { "NIL", UNIT_NIL },
  { "I0", UNIT_I0 },
  { "I1", UNIT_I1 },
  { "I01", UNIT_I01 },
  { "FM0", UNIT_FM0 },
  { "FM1", UNIT_FM1 },
  { "FM01", UNIT_FM01 },
  { "B0", UNIT_B0 },
  { "B1", UNIT_B1 },
  { "B01", UNIT_B01 },
  { "C", UNIT_C },
  { "MULT_DIV", UNIT_MULT_DIV },
  { "LOAD", UNIT_LOAD },
  { "NUM_UNITS", UNIT_NUM_UNITS },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
{
  { "NONE", FR400_MAJOR_NONE },
  { "I_1", FR400_MAJOR_I_1 },
  { "I_2", FR400_MAJOR_I_2 },
  { "I_3", FR400_MAJOR_I_3 },
  { "I_4", FR400_MAJOR_I_4 },
  { "I_5", FR400_MAJOR_I_5 },
  { "B_1", FR400_MAJOR_B_1 },
  { "B_2", FR400_MAJOR_B_2 },
  { "B_3", FR400_MAJOR_B_3 },
  { "B_4", FR400_MAJOR_B_4 },
  { "B_5", FR400_MAJOR_B_5 },
  { "B_6", FR400_MAJOR_B_6 },
  { "C_1", FR400_MAJOR_C_1 },
  { "C_2", FR400_MAJOR_C_2 },
  { "M_1", FR400_MAJOR_M_1 },
  { "M_2", FR400_MAJOR_M_2 },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
{
  { "NONE", FR500_MAJOR_NONE },
  { "I_1", FR500_MAJOR_I_1 },
  { "I_2", FR500_MAJOR_I_2 },
  { "I_3", FR500_MAJOR_I_3 },
  { "I_4", FR500_MAJOR_I_4 },
  { "I_5", FR500_MAJOR_I_5 },
  { "I_6", FR500_MAJOR_I_6 },
  { "B_1", FR500_MAJOR_B_1 },
  { "B_2", FR500_MAJOR_B_2 },
  { "B_3", FR500_MAJOR_B_3 },
  { "B_4", FR500_MAJOR_B_4 },
  { "B_5", FR500_MAJOR_B_5 },
  { "B_6", FR500_MAJOR_B_6 },
  { "C_1", FR500_MAJOR_C_1 },
  { "C_2", FR500_MAJOR_C_2 },
  { "F_1", FR500_MAJOR_F_1 },
  { "F_2", FR500_MAJOR_F_2 },
  { "F_3", FR500_MAJOR_F_3 },
  { "F_4", FR500_MAJOR_F_4 },
  { "F_5", FR500_MAJOR_F_5 },
  { "F_6", FR500_MAJOR_F_6 },
  { "F_7", FR500_MAJOR_F_7 },
  { "F_8", FR500_MAJOR_F_8 },
  { "M_1", FR500_MAJOR_M_1 },
  { "M_2", FR500_MAJOR_M_2 },
  { "M_3", FR500_MAJOR_M_3 },
  { "M_4", FR500_MAJOR_M_4 },
  { "M_5", FR500_MAJOR_M_5 },
  { "M_6", FR500_MAJOR_M_6 },
  { "M_7", FR500_MAJOR_M_7 },
  { "M_8", FR500_MAJOR_M_8 },
  { 0, 0 }
};

const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  { "PC", &bool_attr[0], &bool_attr[0] },
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
  { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
  { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  { "PBB", &bool_attr[0], &bool_attr[0] },
  { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
  { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] },
  { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
  { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
  { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

/* Instruction set variants.  */

static const CGEN_ISA frv_cgen_isa_table[] = {
  { "frv", 32, 32, 32, 32 },
  { 0, 0, 0, 0, 0 }
};

/* Machine variants.  */

static const CGEN_MACH frv_cgen_mach_table[] = {
  { "frv", "frv", MACH_FRV, 0 },
  { "fr500", "fr500", MACH_FR500, 0 },
  { "tomcat", "tomcat", MACH_TOMCAT, 0 },
  { "fr400", "fr400", MACH_FR400, 0 },
  { "simple", "simple", MACH_SIMPLE, 0 },
  { 0, 0, 0, 0 }
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
{
  { "sp", 1, {0, {0}}, 0, 0 },
  { "fp", 2, {0, {0}}, 0, 0 },
  { "gr0", 0, {0, {0}}, 0, 0 },
  { "gr1", 1, {0, {0}}, 0, 0 },
  { "gr2", 2, {0, {0}}, 0, 0 },
  { "gr3", 3, {0, {0}}, 0, 0 },
  { "gr4", 4, {0, {0}}, 0, 0 },
  { "gr5", 5, {0, {0}}, 0, 0 },
  { "gr6", 6, {0, {0}}, 0, 0 },
  { "gr7", 7, {0, {0}}, 0, 0 },
  { "gr8", 8, {0, {0}}, 0, 0 },
  { "gr9", 9, {0, {0}}, 0, 0 },
  { "gr10", 10, {0, {0}}, 0, 0 },
  { "gr11", 11, {0, {0}}, 0, 0 },
  { "gr12", 12, {0, {0}}, 0, 0 },
  { "gr13", 13, {0, {0}}, 0, 0 },
  { "gr14", 14, {0, {0}}, 0, 0 },
  { "gr15", 15, {0, {0}}, 0, 0 },
  { "gr16", 16, {0, {0}}, 0, 0 },
  { "gr17", 17, {0, {0}}, 0, 0 },
  { "gr18", 18, {0, {0}}, 0, 0 },
  { "gr19", 19, {0, {0}}, 0, 0 },
  { "gr20", 20, {0, {0}}, 0, 0 },
  { "gr21", 21, {0, {0}}, 0, 0 },
  { "gr22", 22, {0, {0}}, 0, 0 },
  { "gr23", 23, {0, {0}}, 0, 0 },
  { "gr24", 24, {0, {0}}, 0, 0 },
  { "gr25", 25, {0, {0}}, 0, 0 },
  { "gr26", 26, {0, {0}}, 0, 0 },
  { "gr27", 27, {0, {0}}, 0, 0 },
  { "gr28", 28, {0, {0}}, 0, 0 },
  { "gr29", 29, {0, {0}}, 0, 0 },
  { "gr30", 30, {0, {0}}, 0, 0 },
  { "gr31", 31, {0, {0}}, 0, 0 },
  { "gr32", 32, {0, {0}}, 0, 0 },
  { "gr33", 33, {0, {0}}, 0, 0 },
  { "gr34", 34, {0, {0}}, 0, 0 },
  { "gr35", 35, {0, {0}}, 0, 0 },
  { "gr36", 36, {0, {0}}, 0, 0 },
  { "gr37", 37, {0, {0}}, 0, 0 },
  { "gr38", 38, {0, {0}}, 0, 0 },
  { "gr39", 39, {0, {0}}, 0, 0 },
  { "gr40", 40, {0, {0}}, 0, 0 },
  { "gr41", 41, {0, {0}}, 0, 0 },
  { "gr42", 42, {0, {0}}, 0, 0 },
  { "gr43", 43, {0, {0}}, 0, 0 },
  { "gr44", 44, {0, {0}}, 0, 0 },
  { "gr45", 45, {0, {0}}, 0, 0 },
  { "gr46", 46, {0, {0}}, 0, 0 },
  { "gr47", 47, {0, {0}}, 0, 0 },
  { "gr48", 48, {0, {0}}, 0, 0 },
  { "gr49", 49, {0, {0}}, 0, 0 },
  { "gr50", 50, {0, {0}}, 0, 0 },
  { "gr51", 51, {0, {0}}, 0, 0 },
  { "gr52", 52, {0, {0}}, 0, 0 },
  { "gr53", 53, {0, {0}}, 0, 0 },
  { "gr54", 54, {0, {0}}, 0, 0 },
  { "gr55", 55, {0, {0}}, 0, 0 },
  { "gr56", 56, {0, {0}}, 0, 0 },
  { "gr57", 57, {0, {0}}, 0, 0 },
  { "gr58", 58, {0, {0}}, 0, 0 },
  { "gr59", 59, {0, {0}}, 0, 0 },
  { "gr60", 60, {0, {0}}, 0, 0 },
  { "gr61", 61, {0, {0}}, 0, 0 },
  { "gr62", 62, {0, {0}}, 0, 0 },
  { "gr63", 63, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_gr_names =
{
  & frv_cgen_opval_gr_names_entries[0],
  66,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
{
  { "fr0", 0, {0, {0}}, 0, 0 },
  { "fr1", 1, {0, {0}}, 0, 0 },
  { "fr2", 2, {0, {0}}, 0, 0 },
  { "fr3", 3, {0, {0}}, 0, 0 },
  { "fr4", 4, {0, {0}}, 0, 0 },
  { "fr5", 5, {0, {0}}, 0, 0 },
  { "fr6", 6, {0, {0}}, 0, 0 },
  { "fr7", 7, {0, {0}}, 0, 0 },
  { "fr8", 8, {0, {0}}, 0, 0 },
  { "fr9", 9, {0, {0}}, 0, 0 },
  { "fr10", 10, {0, {0}}, 0, 0 },
  { "fr11", 11, {0, {0}}, 0, 0 },
  { "fr12", 12, {0, {0}}, 0, 0 },
  { "fr13", 13, {0, {0}}, 0, 0 },
  { "fr14", 14, {0, {0}}, 0, 0 },
  { "fr15", 15, {0, {0}}, 0, 0 },
  { "fr16", 16, {0, {0}}, 0, 0 },
  { "fr17", 17, {0, {0}}, 0, 0 },
  { "fr18", 18, {0, {0}}, 0, 0 },
  { "fr19", 19, {0, {0}}, 0, 0 },
  { "fr20", 20, {0, {0}}, 0, 0 },
  { "fr21", 21, {0, {0}}, 0, 0 },
  { "fr22", 22, {0, {0}}, 0, 0 },
  { "fr23", 23, {0, {0}}, 0, 0 },
  { "fr24", 24, {0, {0}}, 0, 0 },
  { "fr25", 25, {0, {0}}, 0, 0 },
  { "fr26", 26, {0, {0}}, 0, 0 },
  { "fr27", 27, {0, {0}}, 0, 0 },
  { "fr28", 28, {0, {0}}, 0, 0 },
  { "fr29", 29, {0, {0}}, 0, 0 },
  { "fr30", 30, {0, {0}}, 0, 0 },
  { "fr31", 31, {0, {0}}, 0, 0 },
  { "fr32", 32, {0, {0}}, 0, 0 },
  { "fr33", 33, {0, {0}}, 0, 0 },
  { "fr34", 34, {0, {0}}, 0, 0 },
  { "fr35", 35, {0, {0}}, 0, 0 },
  { "fr36", 36, {0, {0}}, 0, 0 },
  { "fr37", 37, {0, {0}}, 0, 0 },
  { "fr38", 38, {0, {0}}, 0, 0 },
  { "fr39", 39, {0, {0}}, 0, 0 },
  { "fr40", 40, {0, {0}}, 0, 0 },
  { "fr41", 41, {0, {0}}, 0, 0 },
  { "fr42", 42, {0, {0}}, 0, 0 },
  { "fr43", 43, {0, {0}}, 0, 0 },
  { "fr44", 44, {0, {0}}, 0, 0 },
  { "fr45", 45, {0, {0}}, 0, 0 },
  { "fr46", 46, {0, {0}}, 0, 0 },
  { "fr47", 47, {0, {0}}, 0, 0 },
  { "fr48", 48, {0, {0}}, 0, 0 },
  { "fr49", 49, {0, {0}}, 0, 0 },
  { "fr50", 50, {0, {0}}, 0, 0 },
  { "fr51", 51, {0, {0}}, 0, 0 },
  { "fr52", 52, {0, {0}}, 0, 0 },
  { "fr53", 53, {0, {0}}, 0, 0 },
  { "fr54", 54, {0, {0}}, 0, 0 },
  { "fr55", 55, {0, {0}}, 0, 0 },
  { "fr56", 56, {0, {0}}, 0, 0 },
  { "fr57", 57, {0, {0}}, 0, 0 },
  { "fr58", 58, {0, {0}}, 0, 0 },
  { "fr59", 59, {0, {0}}, 0, 0 },
  { "fr60", 60, {0, {0}}, 0, 0 },
  { "fr61", 61, {0, {0}}, 0, 0 },
  { "fr62", 62, {0, {0}}, 0, 0 },
  { "fr63", 63, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_fr_names =
{
  & frv_cgen_opval_fr_names_entries[0],
  64,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
{
  { "cpr0", 0, {0, {0}}, 0, 0 },
  { "cpr1", 1, {0, {0}}, 0, 0 },
  { "cpr2", 2, {0, {0}}, 0, 0 },
  { "cpr3", 3, {0, {0}}, 0, 0 },
  { "cpr4", 4, {0, {0}}, 0, 0 },
  { "cpr5", 5, {0, {0}}, 0, 0 },
  { "cpr6", 6, {0, {0}}, 0, 0 },
  { "cpr7", 7, {0, {0}}, 0, 0 },
  { "cpr8", 8, {0, {0}}, 0, 0 },
  { "cpr9", 9, {0, {0}}, 0, 0 },
  { "cpr10", 10, {0, {0}}, 0, 0 },
  { "cpr11", 11, {0, {0}}, 0, 0 },
  { "cpr12", 12, {0, {0}}, 0, 0 },
  { "cpr13", 13, {0, {0}}, 0, 0 },
  { "cpr14", 14, {0, {0}}, 0, 0 },
  { "cpr15", 15, {0, {0}}, 0, 0 },
  { "cpr16", 16, {0, {0}}, 0, 0 },
  { "cpr17", 17, {0, {0}}, 0, 0 },
  { "cpr18", 18, {0, {0}}, 0, 0 },
  { "cpr19", 19, {0, {0}}, 0, 0 },
  { "cpr20", 20, {0, {0}}, 0, 0 },
  { "cpr21", 21, {0, {0}}, 0, 0 },
  { "cpr22", 22, {0, {0}}, 0, 0 },
  { "cpr23", 23, {0, {0}}, 0, 0 },
  { "cpr24", 24, {0, {0}}, 0, 0 },
  { "cpr25", 25, {0, {0}}, 0, 0 },
  { "cpr26", 26, {0, {0}}, 0, 0 },
  { "cpr27", 27, {0, {0}}, 0, 0 },
  { "cpr28", 28, {0, {0}}, 0, 0 },
  { "cpr29", 29, {0, {0}}, 0, 0 },
  { "cpr30", 30, {0, {0}}, 0, 0 },
  { "cpr31", 31, {0, {0}}, 0, 0 },
  { "cpr32", 32, {0, {0}}, 0, 0 },
  { "cpr33", 33, {0, {0}}, 0, 0 },
  { "cpr34", 34, {0, {0}}, 0, 0 },
  { "cpr35", 35, {0, {0}}, 0, 0 },
  { "cpr36", 36, {0, {0}}, 0, 0 },
  { "cpr37", 37, {0, {0}}, 0, 0 },
  { "cpr38", 38, {0, {0}}, 0, 0 },
  { "cpr39", 39, {0, {0}}, 0, 0 },
  { "cpr40", 40, {0, {0}}, 0, 0 },
  { "cpr41", 41, {0, {0}}, 0, 0 },
  { "cpr42", 42, {0, {0}}, 0, 0 },
  { "cpr43", 43, {0, {0}}, 0, 0 },
  { "cpr44", 44, {0, {0}}, 0, 0 },
  { "cpr45", 45, {0, {0}}, 0, 0 },
  { "cpr46", 46, {0, {0}}, 0, 0 },
  { "cpr47", 47, {0, {0}}, 0, 0 },
  { "cpr48", 48, {0, {0}}, 0, 0 },
  { "cpr49", 49, {0, {0}}, 0, 0 },
  { "cpr50", 50, {0, {0}}, 0, 0 },
  { "cpr51", 51, {0, {0}}, 0, 0 },
  { "cpr52", 52, {0, {0}}, 0, 0 },
  { "cpr53", 53, {0, {0}}, 0, 0 },
  { "cpr54", 54, {0, {0}}, 0, 0 },
  { "cpr55", 55, {0, {0}}, 0, 0 },
  { "cpr56", 56, {0, {0}}, 0, 0 },
  { "cpr57", 57, {0, {0}}, 0, 0 },
  { "cpr58", 58, {0, {0}}, 0, 0 },
  { "cpr59", 59, {0, {0}}, 0, 0 },
  { "cpr60", 60, {0, {0}}, 0, 0 },
  { "cpr61", 61, {0, {0}}, 0, 0 },
  { "cpr62", 62, {0, {0}}, 0, 0 },
  { "cpr63", 63, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_cpr_names =
{
  & frv_cgen_opval_cpr_names_entries[0],
  64,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
{
  { "psr", 0, {0, {0}}, 0, 0 },
  { "pcsr", 1, {0, {0}}, 0, 0 },
  { "bpcsr", 2, {0, {0}}, 0, 0 },
  { "tbr", 3, {0, {0}}, 0, 0 },
  { "bpsr", 4, {0, {0}}, 0, 0 },
  { "hsr0", 16, {0, {0}}, 0, 0 },
  { "hsr1", 17, {0, {0}}, 0, 0 },
  { "hsr2", 18, {0, {0}}, 0, 0 },
  { "hsr3", 19, {0, {0}}, 0, 0 },
  { "hsr4", 20, {0, {0}}, 0, 0 },
  { "hsr5", 21, {0, {0}}, 0, 0 },
  { "hsr6", 22, {0, {0}}, 0, 0 },
  { "hsr7", 23, {0, {0}}, 0, 0 },
  { "hsr8", 24, {0, {0}}, 0, 0 },
  { "hsr9", 25, {0, {0}}, 0, 0 },
  { "hsr10", 26, {0, {0}}, 0, 0 },
  { "hsr11", 27, {0, {0}}, 0, 0 },
  { "hsr12", 28, {0, {0}}, 0, 0 },
  { "hsr13", 29, {0, {0}}, 0, 0 },
  { "hsr14", 30, {0, {0}}, 0, 0 },
  { "hsr15", 31, {0, {0}}, 0, 0 },
  { "hsr16", 32, {0, {0}}, 0, 0 },
  { "hsr17", 33, {0, {0}}, 0, 0 },
  { "hsr18", 34, {0, {0}}, 0, 0 },
  { "hsr19", 35, {0, {0}}, 0, 0 },
  { "hsr20", 36, {0, {0}}, 0, 0 },
  { "hsr21", 37, {0, {0}}, 0, 0 },
  { "hsr22", 38, {0, {0}}, 0, 0 },
  { "hsr23", 39, {0, {0}}, 0, 0 },
  { "hsr24", 40, {0, {0}}, 0, 0 },
  { "hsr25", 41, {0, {0}}, 0, 0 },
  { "hsr26", 42, {0, {0}}, 0, 0 },
  { "hsr27", 43, {0, {0}}, 0, 0 },
  { "hsr28", 44, {0, {0}}, 0, 0 },
  { "hsr29", 45, {0, {0}}, 0, 0 },
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  { "iampr26", 1754, {0, {0}}, 0, 0 },
  { "iampr27", 1755, {0, {0}}, 0, 0 },
  { "iampr28", 1756, {0, {0}}, 0, 0 },
  { "iampr29", 1757, {0, {0}}, 0, 0 },
  { "iampr30", 1758, {0, {0}}, 0, 0 },
  { "iampr31", 1759, {0, {0}}, 0, 0 },
  { "iampr32", 1760, {0, {0}}, 0, 0 },
  { "iampr33", 1761, {0, {0}}, 0, 0 },
  { "iampr34", 1762, {0, {0}}, 0, 0 },
  { "iampr35", 1763, {0, {0}}, 0, 0 },
  { "iampr36", 1764, {0, {0}}, 0, 0 },
  { "iampr37", 1765, {0, {0}}, 0, 0 },
  { "iampr38", 1766, {0, {0}}, 0, 0 },
  { "iampr39", 1767, {0, {0}}, 0, 0 },
  { "iampr40", 1768, {0, {0}}, 0, 0 },
  { "iampr41", 1769, {0, {0}}, 0, 0 },
  { "iampr42", 1770, {0, {0}}, 0, 0 },
  { "iampr43", 1771, {0, {0}}, 0, 0 },
  { "iampr44", 1772, {0, {0}}, 0, 0 },
  { "iampr45", 1773, {0, {0}}, 0, 0 },
  { "iampr46", 1774, {0, {0}}, 0, 0 },
  { "iampr47", 1775, {0, {0}}, 0, 0 },
  { "iampr48", 1776, {0, {0}}, 0, 0 },
  { "iampr49", 1777, {0, {0}}, 0, 0 },
  { "iampr50", 1778, {0, {0}}, 0, 0 },
  { "iampr51", 1779, {0, {0}}, 0, 0 },
  { "iampr52", 1780, {0, {0}}, 0, 0 },
  { "iampr53", 1781, {0, {0}}, 0, 0 },
  { "iampr54", 1782, {0, {0}}, 0, 0 },
  { "iampr55", 1783, {0, {0}}, 0, 0 },
  { "iampr56", 1784, {0, {0}}, 0, 0 },
  { "iampr57", 1785, {0, {0}}, 0, 0 },
  { "iampr58", 1786, {0, {0}}, 0, 0 },
  { "iampr59", 1787, {0, {0}}, 0, 0 },
  { "iampr60", 1788, {0, {0}}, 0, 0 },
  { "iampr61", 1789, {0, {0}}, 0, 0 },
  { "iampr62", 1790, {0, {0}}, 0, 0 },
  { "iampr63", 1791, {0, {0}}, 0, 0 },
  { "damlr0", 1792, {0, {0}}, 0, 0 },
  { "damlr1", 1793, {0, {0}}, 0, 0 },
  { "damlr2", 1794, {0, {0}}, 0, 0 },
  { "damlr3", 1795, {0, {0}}, 0, 0 },
  { "damlr4", 1796, {0, {0}}, 0, 0 },
  { "damlr5", 1797, {0, {0}}, 0, 0 },
  { "damlr6", 1798, {0, {0}}, 0, 0 },
  { "damlr7", 1799, {0, {0}}, 0, 0 },
  { "damlr8", 1800, {0, {0}}, 0, 0 },
  { "damlr9", 1801, {0, {0}}, 0, 0 },
  { "damlr10", 1802, {0, {0}}, 0, 0 },
  { "damlr11", 1803, {0, {0}}, 0, 0 },
  { "damlr12", 1804, {0, {0}}, 0, 0 },
  { "damlr13", 1805, {0, {0}}, 0, 0 },
  { "damlr14", 1806, {0, {0}}, 0, 0 },
  { "damlr15", 1807, {0, {0}}, 0, 0 },
  { "damlr16", 1808, {0, {0}}, 0, 0 },
  { "damlr17", 1809, {0, {0}}, 0, 0 },
  { "damlr18", 1810, {0, {0}}, 0, 0 },
  { "damlr19", 1811, {0, {0}}, 0, 0 },
  { "damlr20", 1812, {0, {0}}, 0, 0 },
  { "damlr21", 1813, {0, {0}}, 0, 0 },
  { "damlr22", 1814, {0, {0}}, 0, 0 },
  { "damlr23", 1815, {0, {0}}, 0, 0 },
  { "damlr24", 1816, {0, {0}}, 0, 0 },
  { "damlr25", 1817, {0, {0}}, 0, 0 },
  { "damlr26", 1818, {0, {0}}, 0, 0 },
  { "damlr27", 1819, {0, {0}}, 0, 0 },
  { "damlr28", 1820, {0, {0}}, 0, 0 },
  { "damlr29", 1821, {0, {0}}, 0, 0 },
  { "damlr30", 1822, {0, {0}}, 0, 0 },
  { "damlr31", 1823, {0, {0}}, 0, 0 },
  { "damlr32", 1824, {0, {0}}, 0, 0 },
  { "damlr33", 1825, {0, {0}}, 0, 0 },
  { "damlr34", 1826, {0, {0}}, 0, 0 },
  { "damlr35", 1827, {0, {0}}, 0, 0 },
  { "damlr36", 1828, {0, {0}}, 0, 0 },
  { "damlr37", 1829, {0, {0}}, 0, 0 },
  { "damlr38", 1830, {0, {0}}, 0, 0 },
  { "damlr39", 1831, {0, {0}}, 0, 0 },
  { "damlr40", 1832, {0, {0}}, 0, 0 },
  { "damlr41", 1833, {0, {0}}, 0, 0 },
  { "damlr42", 1834, {0, {0}}, 0, 0 },
  { "damlr43", 1835, {0, {0}}, 0, 0 },
  { "damlr44", 1836, {0, {0}}, 0, 0 },
  { "damlr45", 1837, {0, {0}}, 0, 0 },
  { "damlr46", 1838, {0, {0}}, 0, 0 },
  { "damlr47", 1839, {0, {0}}, 0, 0 },
  { "damlr48", 1840, {0, {0}}, 0, 0 },
  { "damlr49", 1841, {0, {0}}, 0, 0 },
  { "damlr50", 1842, {0, {0}}, 0, 0 },
  { "damlr51", 1843, {0, {0}}, 0, 0 },
  { "damlr52", 1844, {0, {0}}, 0, 0 },
  { "damlr53", 1845, {0, {0}}, 0, 0 },
  { "damlr54", 1846, {0, {0}}, 0, 0 },
  { "damlr55", 1847, {0, {0}}, 0, 0 },
  { "damlr56", 1848, {0, {0}}, 0, 0 },
  { "damlr57", 1849, {0, {0}}, 0, 0 },
  { "damlr58", 1850, {0, {0}}, 0, 0 },
  { "damlr59", 1851, {0, {0}}, 0, 0 },
  { "damlr60", 1852, {0, {0}}, 0, 0 },
  { "damlr61", 1853, {0, {0}}, 0, 0 },
  { "damlr62", 1854, {0, {0}}, 0, 0 },
  { "damlr63", 1855, {0, {0}}, 0, 0 },
  { "dampr0", 1856, {0, {0}}, 0, 0 },
  { "dampr1", 1857, {0, {0}}, 0, 0 },
  { "dampr2", 1858, {0, {0}}, 0, 0 },
  { "dampr3", 1859, {0, {0}}, 0, 0 },
  { "dampr4", 1860, {0, {0}}, 0, 0 },
  { "dampr5", 1861, {0, {0}}, 0, 0 },
  { "dampr6", 1862, {0, {0}}, 0, 0 },
  { "dampr7", 1863, {0, {0}}, 0, 0 },
  { "dampr8", 1864, {0, {0}}, 0, 0 },
  { "dampr9", 1865, {0, {0}}, 0, 0 },
  { "dampr10", 1866, {0, {0}}, 0, 0 },
  { "dampr11", 1867, {0, {0}}, 0, 0 },
  { "dampr12", 1868, {0, {0}}, 0, 0 },
  { "dampr13", 1869, {0, {0}}, 0, 0 },
  { "dampr14", 1870, {0, {0}}, 0, 0 },
  { "dampr15", 1871, {0, {0}}, 0, 0 },
  { "dampr16", 1872, {0, {0}}, 0, 0 },
  { "dampr17", 1873, {0, {0}}, 0, 0 },
  { "dampr18", 1874, {0, {0}}, 0, 0 },
  { "dampr19", 1875, {0, {0}}, 0, 0 },
  { "dampr20", 1876, {0, {0}}, 0, 0 },
  { "dampr21", 1877, {0, {0}}, 0, 0 },
  { "dampr22", 1878, {0, {0}}, 0, 0 },
  { "dampr23", 1879, {0, {0}}, 0, 0 },
  { "dampr24", 1880, {0, {0}}, 0, 0 },
  { "dampr25", 1881, {0, {0}}, 0, 0 },
  { "dampr26", 1882, {0, {0}}, 0, 0 },
  { "dampr27", 1883, {0, {0}}, 0, 0 },
  { "dampr28", 1884, {0, {0}}, 0, 0 },
  { "dampr29", 1885, {0, {0}}, 0, 0 },
  { "dampr30", 1886, {0, {0}}, 0, 0 },
  { "dampr31", 1887, {0, {0}}, 0, 0 },
  { "dampr32", 1888, {0, {0}}, 0, 0 },
  { "dampr33", 1889, {0, {0}}, 0, 0 },
  { "dampr34", 1890, {0, {0}}, 0, 0 },
  { "dampr35", 1891, {0, {0}}, 0, 0 },
  { "dampr36", 1892, {0, {0}}, 0, 0 },
  { "dampr37", 1893, {0, {0}}, 0, 0 },
  { "dampr38", 1894, {0, {0}}, 0, 0 },
  { "dampr39", 1895, {0, {0}}, 0, 0 },
  { "dampr40", 1896, {0, {0}}, 0, 0 },
  { "dampr41", 1897, {0, {0}}, 0, 0 },
  { "dampr42", 1898, {0, {0}}, 0, 0 },
  { "dampr43", 1899, {0, {0}}, 0, 0 },
  { "dampr44", 1900, {0, {0}}, 0, 0 },
  { "dampr45", 1901, {0, {0}}, 0, 0 },
  { "dampr46", 1902, {0, {0}}, 0, 0 },
  { "dampr47", 1903, {0, {0}}, 0, 0 },
  { "dampr48", 1904, {0, {0}}, 0, 0 },
  { "dampr49", 1905, {0, {0}}, 0, 0 },
  { "dampr50", 1906, {0, {0}}, 0, 0 },
  { "dampr51", 1907, {0, {0}}, 0, 0 },
  { "dampr52", 1908, {0, {0}}, 0, 0 },
  { "dampr53", 1909, {0, {0}}, 0, 0 },
  { "dampr54", 1910, {0, {0}}, 0, 0 },
  { "dampr55", 1911, {0, {0}}, 0, 0 },
  { "dampr56", 1912, {0, {0}}, 0, 0 },
  { "dampr57", 1913, {0, {0}}, 0, 0 },
  { "dampr58", 1914, {0, {0}}, 0, 0 },
  { "dampr59", 1915, {0, {0}}, 0, 0 },
  { "dampr60", 1916, {0, {0}}, 0, 0 },
  { "dampr61", 1917, {0, {0}}, 0, 0 },
  { "dampr62", 1918, {0, {0}}, 0, 0 },
  { "dampr63", 1919, {0, {0}}, 0, 0 },
  { "amcr", 1920, {0, {0}}, 0, 0 },
  { "stbar", 1921, {0, {0}}, 0, 0 },
  { "mmcr", 1922, {0, {0}}, 0, 0 },
  { "dcr", 2048, {0, {0}}, 0, 0 },
  { "brr", 2049, {0, {0}}, 0, 0 },
  { "nmar", 2050, {0, {0}}, 0, 0 },
  { "ibar0", 2052, {0, {0}}, 0, 0 },
  { "ibar1", 2053, {0, {0}}, 0, 0 },
  { "ibar2", 2054, {0, {0}}, 0, 0 },
  { "ibar3", 2055, {0, {0}}, 0, 0 },
  { "dbar0", 2056, {0, {0}}, 0, 0 },
  { "dbar1", 2057, {0, {0}}, 0, 0 },
  { "dbar2", 2058, {0, {0}}, 0, 0 },
  { "dbar3", 2059, {0, {0}}, 0, 0 },
  { "dbdr00", 2060, {0, {0}}, 0, 0 },
  { "dbdr01", 2061, {0, {0}}, 0, 0 },
  { "dbdr02", 2062, {0, {0}}, 0, 0 },
  { "dbdr03", 2063, {0, {0}}, 0, 0 },
  { "dbdr10", 2064, {0, {0}}, 0, 0 },
  { "dbdr11", 2065, {0, {0}}, 0, 0 },
  { "dbdr12", 2066, {0, {0}}, 0, 0 },
  { "dbdr13", 2067, {0, {0}}, 0, 0 },
  { "dbdr20", 2068, {0, {0}}, 0, 0 },
  { "dbdr21", 2069, {0, {0}}, 0, 0 },
  { "dbdr22", 2070, {0, {0}}, 0, 0 },
  { "dbdr23", 2071, {0, {0}}, 0, 0 },
  { "dbdr30", 2072, {0, {0}}, 0, 0 },
  { "dbdr31", 2073, {0, {0}}, 0, 0 },
  { "dbdr32", 2074, {0, {0}}, 0, 0 },
  { "dbdr33", 2075, {0, {0}}, 0, 0 },
  { "dbmr00", 2076, {0, {0}}, 0, 0 },
  { "dbmr01", 2077, {0, {0}}, 0, 0 },
  { "dbmr02", 2078, {0, {0}}, 0, 0 },
  { "dbmr03", 2079, {0, {0}}, 0, 0 },
  { "dbmr10", 2080, {0, {0}}, 0, 0 },
  { "dbmr11", 2081, {0, {0}}, 0, 0 },
  { "dbmr12", 2082, {0, {0}}, 0, 0 },
  { "dbmr13", 2083, {0, {0}}, 0, 0 },
  { "dbmr20", 2084, {0, {0}}, 0, 0 },
  { "dbmr21", 2085, {0, {0}}, 0, 0 },
  { "dbmr22", 2086, {0, {0}}, 0, 0 },
  { "dbmr23", 2087, {0, {0}}, 0, 0 },
  { "dbmr30", 2088, {0, {0}}, 0, 0 },
  { "dbmr31", 2089, {0, {0}}, 0, 0 },
  { "dbmr32", 2090, {0, {0}}, 0, 0 },
  { "dbmr33", 2091, {0, {0}}, 0, 0 },
  { "cpcfr", 2092, {0, {0}}, 0, 0 },
  { "cpcr", 2093, {0, {0}}, 0, 0 },
  { "cpsr", 2094, {0, {0}}, 0, 0 },
  { "cpesr0", 2096, {0, {0}}, 0, 0 },
  { "cpesr1", 2097, {0, {0}}, 0, 0 },
  { "cpemr0", 2098, {0, {0}}, 0, 0 },
  { "cpemr1", 2099, {0, {0}}, 0, 0 },
  { "ihsr8", 3848, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_spr_names =
{
  & frv_cgen_opval_spr_names_entries[0],
  1005,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
{
  { "accg0", 0, {0, {0}}, 0, 0 },
  { "accg1", 1, {0, {0}}, 0, 0 },
  { "accg2", 2, {0, {0}}, 0, 0 },
  { "accg3", 3, {0, {0}}, 0, 0 },
  { "accg4", 4, {0, {0}}, 0, 0 },
  { "accg5", 5, {0, {0}}, 0, 0 },
  { "accg6", 6, {0, {0}}, 0, 0 },
  { "accg7", 7, {0, {0}}, 0, 0 },
  { "accg8", 8, {0, {0}}, 0, 0 },
  { "accg9", 9, {0, {0}}, 0, 0 },
  { "accg10", 10, {0, {0}}, 0, 0 },
  { "accg11", 11, {0, {0}}, 0, 0 },
  { "accg12", 12, {0, {0}}, 0, 0 },
  { "accg13", 13, {0, {0}}, 0, 0 },
  { "accg14", 14, {0, {0}}, 0, 0 },
  { "accg15", 15, {0, {0}}, 0, 0 },
  { "accg16", 16, {0, {0}}, 0, 0 },
  { "accg17", 17, {0, {0}}, 0, 0 },
  { "accg18", 18, {0, {0}}, 0, 0 },
  { "accg19", 19, {0, {0}}, 0, 0 },
  { "accg20", 20, {0, {0}}, 0, 0 },
  { "accg21", 21, {0, {0}}, 0, 0 },
  { "accg22", 22, {0, {0}}, 0, 0 },
  { "accg23", 23, {0, {0}}, 0, 0 },
  { "accg24", 24, {0, {0}}, 0, 0 },
  { "accg25", 25, {0, {0}}, 0, 0 },
  { "accg26", 26, {0, {0}}, 0, 0 },
  { "accg27", 27, {0, {0}}, 0, 0 },
  { "accg28", 28, {0, {0}}, 0, 0 },
  { "accg29", 29, {0, {0}}, 0, 0 },
  { "accg30", 30, {0, {0}}, 0, 0 },
  { "accg31", 31, {0, {0}}, 0, 0 },
  { "accg32", 32, {0, {0}}, 0, 0 },
  { "accg33", 33, {0, {0}}, 0, 0 },
  { "accg34", 34, {0, {0}}, 0, 0 },
  { "accg35", 35, {0, {0}}, 0, 0 },
  { "accg36", 36, {0, {0}}, 0, 0 },
  { "accg37", 37, {0, {0}}, 0, 0 },
  { "accg38", 38, {0, {0}}, 0, 0 },
  { "accg39", 39, {0, {0}}, 0, 0 },
  { "accg40", 40, {0, {0}}, 0, 0 },
  { "accg41", 41, {0, {0}}, 0, 0 },
  { "accg42", 42, {0, {0}}, 0, 0 },
  { "accg43", 43, {0, {0}}, 0, 0 },
  { "accg44", 44, {0, {0}}, 0, 0 },
  { "accg45", 45, {0, {0}}, 0, 0 },
  { "accg46", 46, {0, {0}}, 0, 0 },
  { "accg47", 47, {0, {0}}, 0, 0 },
  { "accg48", 48, {0, {0}}, 0, 0 },
  { "accg49", 49, {0, {0}}, 0, 0 },
  { "accg50", 50, {0, {0}}, 0, 0 },
  { "accg51", 51, {0, {0}}, 0, 0 },
  { "accg52", 52, {0, {0}}, 0, 0 },
  { "accg53", 53, {0, {0}}, 0, 0 },
  { "accg54", 54, {0, {0}}, 0, 0 },
  { "accg55", 55, {0, {0}}, 0, 0 },
  { "accg56", 56, {0, {0}}, 0, 0 },
  { "accg57", 57, {0, {0}}, 0, 0 },
  { "accg58", 58, {0, {0}}, 0, 0 },
  { "accg59", 59, {0, {0}}, 0, 0 },
  { "accg60", 60, {0, {0}}, 0, 0 },
  { "accg61", 61, {0, {0}}, 0, 0 },
  { "accg62", 62, {0, {0}}, 0, 0 },
  { "accg63", 63, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_accg_names =
{
  & frv_cgen_opval_accg_names_entries[0],
  64,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
{
  { "acc0", 0, {0, {0}}, 0, 0 },
  { "acc1", 1, {0, {0}}, 0, 0 },
  { "acc2", 2, {0, {0}}, 0, 0 },
  { "acc3", 3, {0, {0}}, 0, 0 },
  { "acc4", 4, {0, {0}}, 0, 0 },
  { "acc5", 5, {0, {0}}, 0, 0 },
  { "acc6", 6, {0, {0}}, 0, 0 },
  { "acc7", 7, {0, {0}}, 0, 0 },
  { "acc8", 8, {0, {0}}, 0, 0 },
  { "acc9", 9, {0, {0}}, 0, 0 },
  { "acc10", 10, {0, {0}}, 0, 0 },
  { "acc11", 11, {0, {0}}, 0, 0 },
  { "acc12", 12, {0, {0}}, 0, 0 },
  { "acc13", 13, {0, {0}}, 0, 0 },
  { "acc14", 14, {0, {0}}, 0, 0 },
  { "acc15", 15, {0, {0}}, 0, 0 },
  { "acc16", 16, {0, {0}}, 0, 0 },
  { "acc17", 17, {0, {0}}, 0, 0 },
  { "acc18", 18, {0, {0}}, 0, 0 },
  { "acc19", 19, {0, {0}}, 0, 0 },
  { "acc20", 20, {0, {0}}, 0, 0 },
  { "acc21", 21, {0, {0}}, 0, 0 },
  { "acc22", 22, {0, {0}}, 0, 0 },
  { "acc23", 23, {0, {0}}, 0, 0 },
  { "acc24", 24, {0, {0}}, 0, 0 },
  { "acc25", 25, {0, {0}}, 0, 0 },
  { "acc26", 26, {0, {0}}, 0, 0 },
  { "acc27", 27, {0, {0}}, 0, 0 },
  { "acc28", 28, {0, {0}}, 0, 0 },
  { "acc29", 29, {0, {0}}, 0, 0 },
  { "acc30", 30, {0, {0}}, 0, 0 },
  { "acc31", 31, {0, {0}}, 0, 0 },
  { "acc32", 32, {0, {0}}, 0, 0 },
  { "acc33", 33, {0, {0}}, 0, 0 },
  { "acc34", 34, {0, {0}}, 0, 0 },
  { "acc35", 35, {0, {0}}, 0, 0 },
  { "acc36", 36, {0, {0}}, 0, 0 },
  { "acc37", 37, {0, {0}}, 0, 0 },
  { "acc38", 38, {0, {0}}, 0, 0 },
  { "acc39", 39, {0, {0}}, 0, 0 },
  { "acc40", 40, {0, {0}}, 0, 0 },
  { "acc41", 41, {0, {0}}, 0, 0 },
  { "acc42", 42, {0, {0}}, 0, 0 },
  { "acc43", 43, {0, {0}}, 0, 0 },
  { "acc44", 44, {0, {0}}, 0, 0 },
  { "acc45", 45, {0, {0}}, 0, 0 },
  { "acc46", 46, {0, {0}}, 0, 0 },
  { "acc47", 47, {0, {0}}, 0, 0 },
  { "acc48", 48, {0, {0}}, 0, 0 },
  { "acc49", 49, {0, {0}}, 0, 0 },
  { "acc50", 50, {0, {0}}, 0, 0 },
  { "acc51", 51, {0, {0}}, 0, 0 },
  { "acc52", 52, {0, {0}}, 0, 0 },
  { "acc53", 53, {0, {0}}, 0, 0 },
  { "acc54", 54, {0, {0}}, 0, 0 },
  { "acc55", 55, {0, {0}}, 0, 0 },
  { "acc56", 56, {0, {0}}, 0, 0 },
  { "acc57", 57, {0, {0}}, 0, 0 },
  { "acc58", 58, {0, {0}}, 0, 0 },
  { "acc59", 59, {0, {0}}, 0, 0 },
  { "acc60", 60, {0, {0}}, 0, 0 },
  { "acc61", 61, {0, {0}}, 0, 0 },
  { "acc62", 62, {0, {0}}, 0, 0 },
  { "acc63", 63, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_acc_names =
{
  & frv_cgen_opval_acc_names_entries[0],
  64,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
{
  { "icc0", 0, {0, {0}}, 0, 0 },
  { "icc1", 1, {0, {0}}, 0, 0 },
  { "icc2", 2, {0, {0}}, 0, 0 },
  { "icc3", 3, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_iccr_names =
{
  & frv_cgen_opval_iccr_names_entries[0],
  4,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
{
  { "fcc0", 0, {0, {0}}, 0, 0 },
  { "fcc1", 1, {0, {0}}, 0, 0 },
  { "fcc2", 2, {0, {0}}, 0, 0 },
  { "fcc3", 3, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_fccr_names =
{
  & frv_cgen_opval_fccr_names_entries[0],
  4,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
{
  { "cc0", 0, {0, {0}}, 0, 0 },
  { "cc1", 1, {0, {0}}, 0, 0 },
  { "cc2", 2, {0, {0}}, 0, 0 },
  { "cc3", 3, {0, {0}}, 0, 0 },
  { "cc4", 4, {0, {0}}, 0, 0 },
  { "cc5", 5, {0, {0}}, 0, 0 },
  { "cc6", 6, {0, {0}}, 0, 0 },
  { "cc7", 7, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_cccr_names =
{
  & frv_cgen_opval_cccr_names_entries[0],
  8,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
{
  { "", 1, {0, {0}}, 0, 0 },
  { ".p", 0, {0, {0}}, 0, 0 },
  { ".P", 0, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_h_pack =
{
  & frv_cgen_opval_h_pack_entries[0],
  3,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
{
  { "", 2, {0, {0}}, 0, 0 },
  { "", 0, {0, {0}}, 0, 0 },
  { "", 1, {0, {0}}, 0, 0 },
  { "", 3, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
{
  & frv_cgen_opval_h_hint_taken_entries[0],
  4,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
{
  { "", 0, {0, {0}}, 0, 0 },
  { "", 1, {0, {0}}, 0, 0 },
  { "", 2, {0, {0}}, 0, 0 },
  { "", 3, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
{
  & frv_cgen_opval_h_hint_not_taken_entries[0],
  4,
  0, 0, 0, 0, ""
};


/* The hardware table.  */

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_HW_##a)
#else
#define A(a) (1 << CGEN_HW_/**/a)
#endif

const CGEN_HW_ENTRY frv_cgen_hw_table[] =
{
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
  { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
  { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
  { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
  { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
  { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
};

#undef A


/* The instruction field table.  */

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_IFLD_##a)
#else
#define A(a) (1 << CGEN_IFLD_/**/a)
#endif

const CGEN_IFLD frv_cgen_ifld_table[] =
{
  { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
  { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
  { 0, 0, 0, 0, 0, 0, {0, {0}} }
};

#undef A


/* multi ifield declarations */

const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];


/* multi ifield definitions */

const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
{
    { 0, &(frv_cgen_ifld_table[46]) },
    { 0, &(frv_cgen_ifld_table[47]) },
    {0,0}
};
const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
{
    { 0, &(frv_cgen_ifld_table[58]) },
    { 0, &(frv_cgen_ifld_table[59]) },
    {0,0}
};
const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
{
    { 0, &(frv_cgen_ifld_table[61]) },
    { 0, &(frv_cgen_ifld_table[62]) },
    {0,0}
};

/* The operand table.  */

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_OPERAND_##a)
#else
#define A(a) (1 << CGEN_OPERAND_/**/a)
#endif
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define OPERAND(op) FRV_OPERAND_##op
#else
#define OPERAND(op) FRV_OPERAND_/**/op
#endif

const CGEN_OPERAND frv_cgen_operand_table[] =
{
/* pc: program counter */
  { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
    { 0, &(frv_cgen_ifld_table[0]) }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* pack: packing bit */
  { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
    { 0, &(frv_cgen_ifld_table[2]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* GRi: source register 1 */
  { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
    { 0, &(frv_cgen_ifld_table[8]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* GRj: source register 2 */
  { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
    { 0, &(frv_cgen_ifld_table[9]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* GRk: destination register */
  { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
    { 0, &(frv_cgen_ifld_table[10]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* GRkhi: destination register */
  { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
    { 0, &(frv_cgen_ifld_table[10]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* GRklo: destination register */
  { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
    { 0, &(frv_cgen_ifld_table[10]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* GRdoublek: destination register */
  { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
    { 0, &(frv_cgen_ifld_table[10]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ACC40Si: signed accumulator */
  { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
    { 0, &(frv_cgen_ifld_table[19]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ACC40Ui: unsigned accumulator */
  { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
    { 0, &(frv_cgen_ifld_table[20]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ACC40Sk: target accumulator */
  { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
    { 0, &(frv_cgen_ifld_table[21]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ACC40Uk: target accumulator */
  { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
    { 0, &(frv_cgen_ifld_table[22]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ACCGi: source register */
  { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
    { 0, &(frv_cgen_ifld_table[17]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ACCGk: target register */
  { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
    { 0, &(frv_cgen_ifld_table[18]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* CPRi: source register */
  { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
    { 0, &(frv_cgen_ifld_table[14]) }, 
    { 0, { (1<<MACH_FRV) } }  },
/* CPRj: source register */
  { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
    { 0, &(frv_cgen_ifld_table[15]) }, 
    { 0, { (1<<MACH_FRV) } }  },
/* CPRk: destination register */
  { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
    { 0, &(frv_cgen_ifld_table[16]) }, 
    { 0, { (1<<MACH_FRV) } }  },
/* CPRdoublek: destination register */
  { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
    { 0, &(frv_cgen_ifld_table[16]) }, 
    { 0, { (1<<MACH_FRV) } }  },
/* FRinti: source register 1 */
  { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
    { 0, &(frv_cgen_ifld_table[11]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRintj: source register 2 */
  { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
    { 0, &(frv_cgen_ifld_table[12]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRintk: target register */
  { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
    { 0, &(frv_cgen_ifld_table[13]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRi: source register 1 */
  { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
    { 0, &(frv_cgen_ifld_table[11]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRj: source register 2 */
  { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
    { 0, &(frv_cgen_ifld_table[12]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRk: destination register */
  { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
    { 0, &(frv_cgen_ifld_table[13]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRkhi: destination register */
  { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
    { 0, &(frv_cgen_ifld_table[13]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRklo: destination register */
  { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
    { 0, &(frv_cgen_ifld_table[13]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRdoublei: source register 1 */
  { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
    { 0, &(frv_cgen_ifld_table[11]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRdoublej: source register 2 */
  { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
    { 0, &(frv_cgen_ifld_table[12]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FRdoublek: target register */
  { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
    { 0, &(frv_cgen_ifld_table[13]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* CRi: source register 1 */
  { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
    { 0, &(frv_cgen_ifld_table[23]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* CRj: source register 2 */
  { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
    { 0, &(frv_cgen_ifld_table[24]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* CRj_int: destination register */
  { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
    { 0, &(frv_cgen_ifld_table[27]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* CRj_float: destination register */
  { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
    { 0, &(frv_cgen_ifld_table[28]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* CRk: destination register */
  { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
    { 0, &(frv_cgen_ifld_table[25]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* CCi: condition   register */
  { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
    { 0, &(frv_cgen_ifld_table[26]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ICCi_1: condition   register */
  { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
    { 0, &(frv_cgen_ifld_table[29]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ICCi_2: condition   register */
  { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
    { 0, &(frv_cgen_ifld_table[30]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* ICCi_3: condition   register */
  { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
    { 0, &(frv_cgen_ifld_table[31]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FCCi_1: condition   register */
  { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
    { 0, &(frv_cgen_ifld_table[32]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FCCi_2: condition   register */
  { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
    { 0, &(frv_cgen_ifld_table[33]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FCCi_3: condition   register */
  { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
    { 0, &(frv_cgen_ifld_table[34]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* FCCk: condition   register */
  { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
    { 0, &(frv_cgen_ifld_table[35]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* eir: exception insn reg */
  { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
    { 0, &(frv_cgen_ifld_table[36]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* s10: 10 bit signed immediate */
  { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
    { 0, &(frv_cgen_ifld_table[37]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* u16: 16 bit unsigned immediate */
  { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
    { 0, &(frv_cgen_ifld_table[40]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* s16: 16 bit signed   immediate */
  { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
    { 0, &(frv_cgen_ifld_table[41]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* s6: 6  bit signed   immediate */
  { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
    { 0, &(frv_cgen_ifld_table[42]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* s6_1: 6  bit signed   immediate */
  { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
    { 0, &(frv_cgen_ifld_table[43]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* u6: 6  bit unsigned immediate */
  { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
    { 0, &(frv_cgen_ifld_table[44]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* s5: 5  bit signed   immediate */
  { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
    { 0, &(frv_cgen_ifld_table[45]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* cond: conditional arithmetic */
  { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
    { 0, &(frv_cgen_ifld_table[50]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* ccond: lr branch condition */
  { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
    { 0, &(frv_cgen_ifld_table[51]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* hint: 2 bit branch predictor */
  { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
    { 0, &(frv_cgen_ifld_table[52]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* hint_taken: 2 bit branch predictor */
  { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
    { 0, &(frv_cgen_ifld_table[52]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* hint_not_taken: 2 bit branch predictor */
  { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
    { 0, &(frv_cgen_ifld_table[52]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* LI: link indicator */
  { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
    { 0, &(frv_cgen_ifld_table[53]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* lock: cache lock indicator */
  { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
    { 0, &(frv_cgen_ifld_table[54]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* debug: debug mode indicator */
  { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
    { 0, &(frv_cgen_ifld_table[55]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* A: all accumulator indicator */
  { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1,
    { 0, &(frv_cgen_ifld_table[56]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* ae: all entries indicator */
  { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
    { 0, &(frv_cgen_ifld_table[57]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* label16: 18 bit pc relative address */
  { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
    { 0, &(frv_cgen_ifld_table[60]) }, 
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
/* label24: 26 bit pc relative address */
  { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
    { 2, &(FRV_F_LABEL24_MULTI_IFIELD[0]) }, 
    { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
/* d12: 12 bit signed immediate */
  { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
    { 0, &(frv_cgen_ifld_table[39]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* s12: 12 bit signed immediate */
  { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
    { 0, &(frv_cgen_ifld_table[39]) }, 
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* u12: 12 bit signed immediate */
  { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
    { 2, &(FRV_F_U12_MULTI_IFIELD[0]) }, 
    { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
/* spr: special purpose register */
  { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
    { 2, &(FRV_F_SPR_MULTI_IFIELD[0]) }, 
    { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
/* ulo16: 16 bit unsigned immediate, for #lo() */
  { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
    { 0, &(frv_cgen_ifld_table[40]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* slo16: 16 bit unsigned immediate, for #lo() */
  { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
    { 0, &(frv_cgen_ifld_table[41]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* uhi16: 16 bit unsigned immediate, for #hi() */
  { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
    { 0, &(frv_cgen_ifld_table[40]) }, 
    { 0, { (1<<MACH_BASE) } }  },
/* psr_esr: PSR.ESR bit */
  { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* psr_s: PSR.S   bit */
  { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* psr_ps: PSR.PS  bit */
  { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* psr_et: PSR.ET  bit */
  { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* bpsr_bs: BPSR.BS  bit */
  { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* bpsr_bet: BPSR.BET bit */
  { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* tbr_tba: TBR.TBA */
  { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* tbr_tt: TBR.TT */
  { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
    { 0, 0 }, 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
  { 0, 0, 0, 0, 0, {0, {0}} }
};

#undef A


/* The instruction table.  */

#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_INSN_##a)
#else
#define A(a) (1 << CGEN_INSN_/**/a)
#endif

static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
{
  /* Special null first entry.
     A `num' value of zero is thus invalid.
     Also, the special `invalid' insn resides here.  */
  { 0, 0, 0, 0, {0, {0}} },
/* add$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_ADD, "add", "add", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sub$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_SUB, "sub", "sub", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* and$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_AND, "and", "and", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* or$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_OR, "or", "or", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* xor$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_XOR, "xor", "xor", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* not$pack $GRj,$GRk */
  {
    FRV_INSN_NOT, "not", "not", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sdiv$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_SDIV, "sdiv", "sdiv", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* nsdiv$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
  },
/* udiv$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_UDIV, "udiv", "udiv", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* nudiv$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
  },
/* smul$pack $GRi,$GRj,$GRdoublek */
  {
    FRV_INSN_SMUL, "smul", "smul", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* umul$pack $GRi,$GRj,$GRdoublek */
  {
    FRV_INSN_UMUL, "umul", "umul", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sll$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_SLL, "sll", "sll", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* srl$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_SRL, "srl", "srl", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sra$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_SRA, "sra", "sra", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* scan$pack $GRi,$GRj,$GRk */
  {
    FRV_INSN_SCAN, "scan", "scan", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CADD, "cadd", "cadd", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSUB, "csub", "csub", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CAND, "cand", "cand", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_COR, "cor", "cor", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CXOR, "cxor", "cxor", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cnot$pack $GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CNOT, "cnot", "cnot", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
  {
    FRV_INSN_CSMUL, "csmul", "csmul", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSLL, "csll", "csll", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSRL, "csrl", "csrl", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSRA, "csra", "csra", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSCAN, "cscan", "cscan", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_ADDCC, "addcc", "addcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_SUBCC, "subcc", "subcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_ANDCC, "andcc", "andcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_ORCC, "orcc", "orcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_XORCC, "xorcc", "xorcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_SRACC, "sracc", "sracc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
  {
    FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
  {
    FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
  {
    FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CANDCC, "candcc", "candcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CORCC, "corcc", "corcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
  {
    FRV_INSN_CSRACC, "csracc", "csracc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_ADDX, "addx", "addx", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_SUBX, "subx", "subx", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
  {
    FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* addi$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_ADDI, "addi", "addi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* subi$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_SUBI, "subi", "subi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* andi$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_ANDI, "andi", "andi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* ori$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_ORI, "ori", "ori", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* xori$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_XORI, "xori", "xori", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sdivi$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* nsdivi$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
  },
/* udivi$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_UDIVI, "udivi", "udivi", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* nudivi$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
  },
/* smuli$pack $GRi,$s12,$GRdoublek */
  {
    FRV_INSN_SMULI, "smuli", "smuli", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* umuli$pack $GRi,$s12,$GRdoublek */
  {
    FRV_INSN_UMULI, "umuli", "umuli", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* slli$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_SLLI, "slli", "slli", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* srli$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_SRLI, "srli", "srli", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* srai$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_SRAI, "srai", "srai", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* scani$pack $GRi,$s12,$GRk */
  {
    FRV_INSN_SCANI, "scani", "scani", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_ADDICC, "addicc", "addicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_SUBICC, "subicc", "subicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_ANDICC, "andicc", "andicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_ORICC, "oricc", "oricc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_XORICC, "xoricc", "xoricc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
  {
    FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
  {
    FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_ADDXI, "addxi", "addxi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_SUBXI, "subxi", "subxi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
  {
    FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* cmpb$pack $GRi,$GRj,$ICCi_1 */
  {
    FRV_INSN_CMPB, "cmpb", "cmpb", 32,
    { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
  },
/* cmpba$pack $GRi,$GRj,$ICCi_1 */
  {
    FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
    { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
  },
/* setlo$pack $ulo16,$GRklo */
  {
    FRV_INSN_SETLO, "setlo", "setlo", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* sethi$pack $uhi16,$GRkhi */
  {
    FRV_INSN_SETHI, "sethi", "sethi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* setlos$pack $slo16,$GRk */
  {
    FRV_INSN_SETLOS, "setlos", "setlos", 32,
    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
  },
/* ldsb$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDSB, "ldsb", "ldsb", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldub$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDUB, "ldub", "ldub", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldsh$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDSH, "ldsh", "ldsh", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* lduh$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDUH, "lduh", "lduh", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ld$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LD, "ld", "ld", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldbf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDBF, "ldbf", "ldbf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldhf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDHF, "ldhf", "ldhf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDF, "ldf", "ldf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldc$pack @($GRi,$GRj),$CPRk */
  {
    FRV_INSN_LDC, "ldc", "ldc", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldsb$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldub$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDUB, "nldub", "nldub", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldsh$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nlduh$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nld$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLD, "nld", "nld", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldbf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldhf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDF, "nldf", "nldf", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldd$pack @($GRi,$GRj),$GRdoublek */
  {
    FRV_INSN_LDD, "ldd", "ldd", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* lddf$pack @($GRi,$GRj),$FRdoublek */
  {
    FRV_INSN_LDDF, "lddf", "lddf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* lddc$pack @($GRi,$GRj),$CPRdoublek */
  {
    FRV_INSN_LDDC, "lddc", "lddc", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* nldd$pack @($GRi,$GRj),$GRdoublek */
  {
    FRV_INSN_NLDD, "nldd", "nldd", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nlddf$pack @($GRi,$GRj),$FRdoublek */
  {
    FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldq$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDQ, "ldq", "ldq", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldqf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDQF, "ldqf", "ldqf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldqc$pack @($GRi,$GRj),$CPRk */
  {
    FRV_INSN_LDQC, "ldqc", "ldqc", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldq$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDQ, "nldq", "nldq", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldqf$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldsbu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldubu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldshu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* lduhu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDU, "ldu", "ldu", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* nldsbu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldubu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldshu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nlduhu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDU, "nldu", "nldu", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldbfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldhfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDFU, "ldfu", "ldfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldcu$pack @($GRi,$GRj),$CPRk */
  {
    FRV_INSN_LDCU, "ldcu", "ldcu", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldbfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldhfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* lddu$pack @($GRi,$GRj),$GRdoublek */
  {
    FRV_INSN_LDDU, "lddu", "lddu", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* nlddu$pack @($GRi,$GRj),$GRdoublek */
  {
    FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* lddfu$pack @($GRi,$GRj),$FRdoublek */
  {
    FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* lddcu$pack @($GRi,$GRj),$CPRdoublek */
  {
    FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* nlddfu$pack @($GRi,$GRj),$FRdoublek */
  {
    FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldqu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_LDQU, "ldqu", "ldqu", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldqu$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldqfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldqcu$pack @($GRi,$GRj),$CPRk */
  {
    FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldqfu$pack @($GRi,$GRj),$FRintk */
  {
    FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldsbi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldshi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_LDI, "ldi", "ldi", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldubi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* lduhi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldbfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldhfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* ldfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_LDFI, "ldfi", "ldfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* nldsbi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldubi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldshi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nlduhi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_NLDI, "nldi", "nldi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldbfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldhfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* lddi$pack @($GRi,$d12),$GRdoublek */
  {
    FRV_INSN_LDDI, "lddi", "lddi", 32,
    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* lddfi$pack @($GRi,$d12),$FRdoublek */
  {
    FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* nlddi$pack @($GRi,$d12),$GRdoublek */
  {
    FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nlddfi$pack @($GRi,$d12),$FRdoublek */
  {
    FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldqi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_LDQI, "ldqi", "ldqi", 32,
    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* ldqfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldqi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_NLDQI, "nldqi", "nldqi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* nldqfi$pack @($GRi,$d12),$FRintk */
  {
    FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* stb$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STB, "stb", "stb", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* sth$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STH, "sth", "sth", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* st$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_ST, "st", "st", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stbf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STBF, "stbf", "stbf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* sthf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STHF, "sthf", "sthf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STF, "stf", "stf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stc$pack $CPRk,@($GRi,$GRj) */
  {
    FRV_INSN_STC, "stc", "stc", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* rstb$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTB, "rstb", "rstb", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rsth$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTH, "rsth", "rsth", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rst$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_RST, "rst", "rst", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rstbf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rsthf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rstf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTF, "rstf", "rstf", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* std$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STD, "std", "std", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stdf$pack $FRk,@($GRi,$GRj) */
  {
    FRV_INSN_STDF, "stdf", "stdf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stdc$pack $CPRk,@($GRi,$GRj) */
  {
    FRV_INSN_STDC, "stdc", "stdc", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* rstd$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTD, "rstd", "rstd", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rstdf$pack $FRk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* stq$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STQ, "stq", "stq", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* stqf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STQF, "stqf", "stqf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* stqc$pack $CPRk,@($GRi,$GRj) */
  {
    FRV_INSN_STQC, "stqc", "stqc", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rstq$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTQ, "rstq", "rstq", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* rstqf$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* stbu$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STBU, "stbu", "stbu", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* sthu$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STHU, "sthu", "sthu", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stu$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STU, "stu", "stu", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stbfu$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STBFU, "stbfu", "stbfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* sthfu$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STHFU, "sthfu", "sthfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stfu$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STFU, "stfu", "stfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stcu$pack $CPRk,@($GRi,$GRj) */
  {
    FRV_INSN_STCU, "stcu", "stcu", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stdu$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STDU, "stdu", "stdu", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stdfu$pack $FRk,@($GRi,$GRj) */
  {
    FRV_INSN_STDFU, "stdfu", "stdfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stdcu$pack $CPRk,@($GRi,$GRj) */
  {
    FRV_INSN_STDCU, "stdcu", "stdcu", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stqu$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_STQU, "stqu", "stqu", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* stqfu$pack $FRintk,@($GRi,$GRj) */
  {
    FRV_INSN_STQFU, "stqfu", "stqfu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* stqcu$pack $CPRk,@($GRi,$GRj) */
  {
    FRV_INSN_STQCU, "stqcu", "stqcu", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDUB, "cldub", "cldub", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDUH, "clduh", "clduh", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLD, "cld", "cld", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
  {
    FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
  {
    FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
  {
    FRV_INSN_CLDF, "cldf", "cldf", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
  {
    FRV_INSN_CLDD, "cldd", "cldd", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
  {
    FRV_INSN_CLDDF, "clddf", "clddf", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDQ, "cldq", "cldq", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDU, "cldu", "cldu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
  {
    FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
  {
    FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
  {
    FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
  {
    FRV_INSN_CLDDU, "clddu", "clddu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
  {
    FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
  },
/* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
  },
/* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTB, "cstb", "cstb", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTH, "csth", "csth", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CST, "cst", "cst", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTHF, "csthf", "csthf", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTF, "cstf", "cstf", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTD, "cstd", "cstd", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTQ, "cstq", "cstq", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTHU, "csthu", "csthu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTU, "cstu", "cstu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stbi$pack $GRk,@($GRi,$d12) */
  {
    FRV_INSN_STBI, "stbi", "stbi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* sthi$pack $GRk,@($GRi,$d12) */
  {
    FRV_INSN_STHI, "sthi", "sthi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* sti$pack $GRk,@($GRi,$d12) */
  {
    FRV_INSN_STI, "sti", "sti", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stbfi$pack $FRintk,@($GRi,$d12) */
  {
    FRV_INSN_STBFI, "stbfi", "stbfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* sthfi$pack $FRintk,@($GRi,$d12) */
  {
    FRV_INSN_STHFI, "sthfi", "sthfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stfi$pack $FRintk,@($GRi,$d12) */
  {
    FRV_INSN_STFI, "stfi", "stfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stdi$pack $GRk,@($GRi,$d12) */
  {
    FRV_INSN_STDI, "stdi", "stdi", 32,
    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stdfi$pack $FRk,@($GRi,$d12) */
  {
    FRV_INSN_STDFI, "stdfi", "stdfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
  },
/* stqi$pack $GRk,@($GRi,$d12) */
  {
    FRV_INSN_STQI, "stqi", "stqi", 32,
    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* stqfi$pack $FRintk,@($GRi,$d12) */
  {
    FRV_INSN_STQFI, "stqfi", "stqfi", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
  },
/* swap$pack @($GRi,$GRj),$GRk */
  {
    FRV_INSN_SWAP, "swap", "swap", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* swapi$pack @($GRi,$d12),$GRk */
  {
    FRV_INSN_SWAPI, "swapi", "swapi", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
  {
    FRV_INSN_CSWAP, "cswap", "cswap", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* movgf$pack $GRj,$FRintk */
  {
    FRV_INSN_MOVGF, "movgf", "movgf", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* movfg$pack $FRintk,$GRj */
  {
    FRV_INSN_MOVFG, "movfg", "movfg", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* movgfd$pack $GRj,$FRintk */
  {
    FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* movfgd$pack $FRintk,$GRj */
  {
    FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* movgfq$pack $GRj,$FRintk */
  {
    FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
  },
/* movfgq$pack $FRintk,$GRj */
  {
    FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
  },
/* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
  {
    FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
  {
    FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
  },
/* movgs$pack $GRj,$spr */
  {
    FRV_INSN_MOVGS, "movgs", "movgs", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* movsg$pack $spr,$GRj */
  {
    FRV_INSN_MOVSG, "movsg", "movsg", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* bra$pack $hint_taken$label16 */
  {
    FRV_INSN_BRA, "bra", "bra", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bno$pack$hint_not_taken */
  {
    FRV_INSN_BNO, "bno", "bno", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* beq$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BEQ, "beq", "beq", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bne$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BNE, "bne", "bne", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* ble$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BLE, "ble", "ble", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bgt$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BGT, "bgt", "bgt", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* blt$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BLT, "blt", "blt", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bge$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BGE, "bge", "bge", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bls$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BLS, "bls", "bls", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bhi$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BHI, "bhi", "bhi", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bc$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BC, "bc", "bc", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bnc$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BNC, "bnc", "bnc", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bn$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BN, "bn", "bn", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bp$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BP, "bp", "bp", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bv$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BV, "bv", "bv", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bnv$pack $ICCi_2,$hint,$label16 */
  {
    FRV_INSN_BNV, "bnv", "bnv", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbra$pack $hint_taken$label16 */
  {
    FRV_INSN_FBRA, "fbra", "fbra", 32,
    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbno$pack$hint_not_taken */
  {
    FRV_INSN_FBNO, "fbno", "fbno", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbne$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBNE, "fbne", "fbne", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbeq$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fblg$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBLG, "fblg", "fblg", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbue$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBUE, "fbue", "fbue", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbul$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBUL, "fbul", "fbul", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbge$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBGE, "fbge", "fbge", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fblt$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBLT, "fblt", "fblt", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbuge$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbug$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBUG, "fbug", "fbug", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fble$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBLE, "fble", "fble", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbgt$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBGT, "fbgt", "fbgt", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbule$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBULE, "fbule", "fbule", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbu$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBU, "fbu", "fbu", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* fbo$pack $FCCi_2,$hint,$label16 */
  {
    FRV_INSN_FBO, "fbo", "fbo", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
  },
/* bctrlr$pack $ccond,$hint */
  {
    FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bralr$pack$hint_taken */
  {
    FRV_INSN_BRALR, "bralr", "bralr", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bnolr$pack$hint_not_taken */
  {
    FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* beqlr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bnelr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BNELR, "bnelr", "bnelr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* blelr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BLELR, "blelr", "blelr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bgtlr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bltlr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bgelr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BGELR, "bgelr", "bgelr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* blslr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BLSLR, "blslr", "blslr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bhilr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BHILR, "bhilr", "bhilr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bclr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BCLR, "bclr", "bclr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bnclr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bnlr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BNLR, "bnlr", "bnlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bplr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BPLR, "bplr", "bplr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bvlr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BVLR, "bvlr", "bvlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bnvlr$pack $ICCi_2,$hint */
  {
    FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbralr$pack$hint_taken */
  {
    FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbnolr$pack$hint_not_taken */
  {
    FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbeqlr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbnelr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fblglr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbuelr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbullr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbgelr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbltlr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbugelr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbuglr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fblelr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbgtlr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbulelr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbulr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBULR, "fbulr", "fbulr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* fbolr$pack $FCCi_2,$hint */
  {
    FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
  },
/* bcralr$pack $ccond$hint_taken */
  {
    FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcnolr$pack$hint_not_taken */
  {
    FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bceqlr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcnelr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bclelr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcgtlr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcltlr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcgelr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bclslr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bchilr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcclr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcnclr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcnlr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcplr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcvlr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* bcnvlr$pack $ICCi_2,$ccond,$hint */
  {
    FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbralr$pack $ccond$hint_taken */
  {
    FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbnolr$pack$hint_not_taken */
  {
    FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbeqlr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbnelr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcblglr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbuelr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbullr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbgelr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbltlr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbugelr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbuglr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcblelr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbgtlr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbulelr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbulr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* fcbolr$pack $FCCi_2,$ccond,$hint */
  {
    FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
  },
/* jmpl$pack @($GRi,$GRj) */
  {
    FRV_INSN_JMPL, "jmpl", "jmpl", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
  },
/* calll$pack @($GRi,$GRj) */
  {
    FRV_INSN_CALLL, "calll", "calll", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
  },
/* jmpil$pack @($GRi,$s12) */
  {
    FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
  },
/* callil$pack @($GRi,$s12) */
  {
    FRV_INSN_CALLIL, "callil", "callil", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
  },
/* call$pack $label24 */
  {
    FRV_INSN_CALL, "call", "call", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } }
  },
/* rett$pack $debug */
  {
    FRV_INSN_RETT, "rett", "rett", 32,
    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* rei$pack $eir */
  {
    FRV_INSN_REI, "rei", "rei", 32,
    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } }
  },
/* tra$pack $GRi,$GRj */
  {
    FRV_INSN_TRA, "tra", "tra", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tno$pack */
  {
    FRV_INSN_TNO, "tno", "tno", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* teq$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TEQ, "teq", "teq", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tne$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TNE, "tne", "tne", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tle$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TLE, "tle", "tle", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tgt$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TGT, "tgt", "tgt", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tlt$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TLT, "tlt", "tlt", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tge$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TGE, "tge", "tge", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tls$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TLS, "tls", "tls", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* thi$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_THI, "thi", "thi", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tc$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TC, "tc", "tc", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tnc$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TNC, "tnc", "tnc", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tn$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TN, "tn", "tn", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tp$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TP, "tp", "tp", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tv$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TV, "tv", "tv", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tnv$pack $ICCi_2,$GRi,$GRj */
  {
    FRV_INSN_TNV, "tnv", "tnv", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftra$pack $GRi,$GRj */
  {
    FRV_INSN_FTRA, "ftra", "ftra", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftno$pack */
  {
    FRV_INSN_FTNO, "ftno", "ftno", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftne$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTNE, "ftne", "ftne", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* fteq$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTEQ, "fteq", "fteq", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftlg$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTLG, "ftlg", "ftlg", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftue$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTUE, "ftue", "ftue", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftul$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTUL, "ftul", "ftul", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftge$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTGE, "ftge", "ftge", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftlt$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTLT, "ftlt", "ftlt", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftuge$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftug$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTUG, "ftug", "ftug", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftle$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTLE, "ftle", "ftle", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftgt$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTGT, "ftgt", "ftgt", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftule$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTULE, "ftule", "ftule", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftu$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTU, "ftu", "ftu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* fto$pack $FCCi_2,$GRi,$GRj */
  {
    FRV_INSN_FTO, "fto", "fto", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tira$pack $GRi,$s12 */
  {
    FRV_INSN_TIRA, "tira", "tira", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tino$pack */
  {
    FRV_INSN_TINO, "tino", "tino", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tieq$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIEQ, "tieq", "tieq", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tine$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TINE, "tine", "tine", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tile$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TILE, "tile", "tile", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tigt$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIGT, "tigt", "tigt", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tilt$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TILT, "tilt", "tilt", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tige$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIGE, "tige", "tige", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tils$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TILS, "tils", "tils", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tihi$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIHI, "tihi", "tihi", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tic$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIC, "tic", "tic", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tinc$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TINC, "tinc", "tinc", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tin$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIN, "tin", "tin", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tip$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIP, "tip", "tip", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tiv$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TIV, "tiv", "tiv", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* tinv$pack $ICCi_2,$GRi,$s12 */
  {
    FRV_INSN_TINV, "tinv", "tinv", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftira$pack $GRi,$s12 */
  {
    FRV_INSN_FTIRA, "ftira", "ftira", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftino$pack */
  {
    FRV_INSN_FTINO, "ftino", "ftino", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftine$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTINE, "ftine", "ftine", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftieq$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftilg$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTILG, "ftilg", "ftilg", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftiue$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftiul$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftige$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIGE, "ftige", "ftige", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftilt$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTILT, "ftilt", "ftilt", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftiuge$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftiug$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftile$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTILE, "ftile", "ftile", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftigt$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftiule$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftiu$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIU, "ftiu", "ftiu", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* ftio$pack $FCCi_2,$GRi,$s12 */
  {
    FRV_INSN_FTIO, "ftio", "ftio", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* break$pack */
  {
    FRV_INSN_BREAK, "break", "break", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* mtrap$pack */
  {
    FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
  },
/* andcr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_ANDCR, "andcr", "andcr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* orcr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_ORCR, "orcr", "orcr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* xorcr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_XORCR, "xorcr", "xorcr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* nandcr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* norcr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_NORCR, "norcr", "norcr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* andncr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_ANDNCR, "andncr", "andncr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* orncr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_ORNCR, "orncr", "orncr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* nandncr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* norncr$pack $CRi,$CRj,$CRk */
  {
    FRV_INSN_NORNCR, "norncr", "norncr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* notcr$pack $CRj,$CRk */
  {
    FRV_INSN_NOTCR, "notcr", "notcr", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
  },
/* ckra$pack $CRj_int */
  {
    FRV_INSN_CKRA, "ckra", "ckra", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckno$pack $CRj_int */
  {
    FRV_INSN_CKNO, "ckno", "ckno", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckeq$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckne$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKNE, "ckne", "ckne", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckle$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKLE, "ckle", "ckle", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckgt$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKGT, "ckgt", "ckgt", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cklt$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKLT, "cklt", "cklt", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckge$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKGE, "ckge", "ckge", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckls$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKLS, "ckls", "ckls", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckhi$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKHI, "ckhi", "ckhi", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckc$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKC, "ckc", "ckc", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cknc$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKNC, "cknc", "cknc", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckn$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKN, "ckn", "ckn", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckp$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKP, "ckp", "ckp", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ckv$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKV, "ckv", "ckv", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cknv$pack $ICCi_3,$CRj_int */
  {
    FRV_INSN_CKNV, "cknv", "cknv", 32,
    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckra$pack $CRj_float */
  {
    FRV_INSN_FCKRA, "fckra", "fckra", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckno$pack $CRj_float */
  {
    FRV_INSN_FCKNO, "fckno", "fckno", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckne$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKNE, "fckne", "fckne", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckeq$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fcklg$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckue$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKUE, "fckue", "fckue", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckul$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKUL, "fckul", "fckul", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckge$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKGE, "fckge", "fckge", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fcklt$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckuge$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckug$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKUG, "fckug", "fckug", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckle$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKLE, "fckle", "fckle", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckgt$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fckule$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKULE, "fckule", "fckule", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fcku$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKU, "fcku", "fcku", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* fcko$pack $FCCi_3,$CRj_float */
  {
    FRV_INSN_FCKO, "fcko", "fcko", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckra$pack $CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKRA, "cckra", "cckra", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckno$pack $CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKNO, "cckno", "cckno", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKNE, "cckne", "cckne", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKLE, "cckle", "cckle", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKGE, "cckge", "cckge", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKLS, "cckls", "cckls", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKC, "cckc", "cckc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKN, "cckn", "cckn", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKP, "cckp", "cckp", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKV, "cckv", "cckv", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
  {
    FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckra$pack $CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckno$pack $CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
  {
    FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
  },
/* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
  },
/* ccalll$pack @($GRi,$GRj),$CCi,$cond */
  {
    FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
  },
/* ici$pack @($GRi,$GRj) */
  {
    FRV_INSN_ICI, "ici", "ici", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* dci$pack @($GRi,$GRj) */
  {
    FRV_INSN_DCI, "dci", "dci", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* icei$pack @($GRi,$GRj),$ae */
  {
    FRV_INSN_ICEI, "icei", "icei", 32,
    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
  },
/* dcei$pack @($GRi,$GRj),$ae */
  {
    FRV_INSN_DCEI, "dcei", "dcei", 32,
    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
  },
/* dcf$pack @($GRi,$GRj) */
  {
    FRV_INSN_DCF, "dcf", "dcf", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* dcef$pack @($GRi,$GRj),$ae */
  {
    FRV_INSN_DCEF, "dcef", "dcef", 32,
    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
  },
/* witlb$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_WITLB, "witlb", "witlb", 32,
    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
  },
/* wdtlb$pack $GRk,@($GRi,$GRj) */
  {
    FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
  },
/* itlbi$pack @($GRi,$GRj) */
  {
    FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
  },
/* dtlbi$pack @($GRi,$GRj) */
  {
    FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
  },
/* icpl$pack $GRi,$GRj,$lock */
  {
    FRV_INSN_ICPL, "icpl", "icpl", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* dcpl$pack $GRi,$GRj,$lock */
  {
    FRV_INSN_DCPL, "dcpl", "dcpl", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* icul$pack $GRi */
  {
    FRV_INSN_ICUL, "icul", "icul", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* dcul$pack $GRi */
  {
    FRV_INSN_DCUL, "dcul", "dcul", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* bar$pack */
  {
    FRV_INSN_BAR, "bar", "bar", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* membar$pack */
  {
    FRV_INSN_MEMBAR, "membar", "membar", 32,
    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
  },
/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
  {
    FRV_INSN_COP1, "cop1", "cop1", 32,
    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
  },
/* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
  {
    FRV_INSN_COP2, "cop2", "cop2", 32,
    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
  },
/* clrgr$pack $GRk */
  {
    FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* clrfr$pack $FRk */
  {
    FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* clrga$pack */
  {
    FRV_INSN_CLRGA, "clrga", "clrga", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* clrfa$pack */
  {
    FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* commitgr$pack $GRk */
  {
    FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* commitfr$pack $FRk */
  {
    FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* commitga$pack */
  {
    FRV_INSN_COMMITGA, "commitga", "commitga", 32,
    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* commitfa$pack */
  {
    FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
  },
/* fitos$pack $FRintj,$FRk */
  {
    FRV_INSN_FITOS, "fitos", "fitos", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fstoi$pack $FRj,$FRintk */
  {
    FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fitod$pack $FRintj,$FRdoublek */
  {
    FRV_INSN_FITOD, "fitod", "fitod", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fdtoi$pack $FRdoublej,$FRintk */
  {
    FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fditos$pack $FRintj,$FRk */
  {
    FRV_INSN_FDITOS, "fditos", "fditos", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fdstoi$pack $FRj,$FRintk */
  {
    FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* nfditos$pack $FRintj,$FRk */
  {
    FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* nfdstoi$pack $FRj,$FRintk */
  {
    FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* cfitos$pack $FRintj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* nfitos$pack $FRintj,$FRk */
  {
    FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* nfstoi$pack $FRj,$FRintk */
  {
    FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fmovs$pack $FRj,$FRk */
  {
    FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fmovd$pack $FRdoublej,$FRdoublek */
  {
    FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fdmovs$pack $FRj,$FRk */
  {
    FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* cfmovs$pack $FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fnegs$pack $FRj,$FRk */
  {
    FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fnegd$pack $FRdoublej,$FRdoublek */
  {
    FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fdnegs$pack $FRj,$FRk */
  {
    FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* cfnegs$pack $FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fabss$pack $FRj,$FRk */
  {
    FRV_INSN_FABSS, "fabss", "fabss", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fabsd$pack $FRdoublej,$FRdoublek */
  {
    FRV_INSN_FABSD, "fabsd", "fabsd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fdabss$pack $FRj,$FRk */
  {
    FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* cfabss$pack $FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
  },
/* fsqrts$pack $FRj,$FRk */
  {
    FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* fdsqrts$pack $FRj,$FRk */
  {
    FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* nfdsqrts$pack $FRj,$FRk */
  {
    FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* fsqrtd$pack $FRdoublej,$FRdoublek */
  {
    FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* nfsqrts$pack $FRj,$FRk */
  {
    FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* fadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FADDS, "fadds", "fadds", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* fsubs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* fmuls$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FMULS, "fmuls", "fmuls", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
  },
/* fdivs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
  {
    FRV_INSN_FADDD, "faddd", "faddd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
  {
    FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
  {
    FRV_INSN_FMULD, "fmuld", "fmuld", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
  },
/* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
  {
    FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
  },
/* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* nfadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* nfsubs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* nfmuls$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
  },
/* nfdivs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
  },
/* fcmps$pack $FRi,$FRj,$FCCi_2 */
  {
    FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
  {
    FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
  {
    FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
  },
/* fdcmps$pack $FRi,$FRj,$FCCi_2 */
  {
    FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* fmadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fmsubs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
  {
    FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
  {
    FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fdmadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* nfdmadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* nfmadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* nfmsubs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fmas$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FMAS, "fmas", "fmas", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fmss$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FMSS, "fmss", "fmss", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fdmas$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fdmss$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* nfdmas$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* nfdmss$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
  {
    FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fmad$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FMAD, "fmad", "fmad", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fmsd$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FMSD, "fmsd", "fmsd", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* nfmas$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* nfmss$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
  },
/* fdadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* fdsubs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* fdmuls$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
  },
/* fddivs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
  },
/* fdsads$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* fdmulcs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
  },
/* nfdmulcs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
  },
/* nfdadds$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* nfdsubs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* nfdmuls$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
  },
/* nfddivs$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
  },
/* nfdsads$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
  {
    FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
  },
/* mhsetlos$pack $u12,$FRklo */
  {
    FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mhsethis$pack $u12,$FRkhi */
  {
    FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mhdsets$pack $u12,$FRintk */
  {
    FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mhsetloh$pack $s5,$FRklo */
  {
    FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mhsethih$pack $s5,$FRkhi */
  {
    FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mhdseth$pack $s5,$FRintk */
  {
    FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mand$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MAND, "mand", "mand", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mor$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MOR, "mor", "mor", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mxor$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MXOR, "mxor", "mxor", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMAND, "cmand", "cmand", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMOR, "cmor", "cmor", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mnot$pack $FRintj,$FRintk */
  {
    FRV_INSN_MNOT, "mnot", "mnot", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mrotli$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mrotri$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mwcut$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* mwcuti$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* mcut$pack $ACC40Si,$FRintj,$FRintk */
  {
    FRV_INSN_MCUT, "mcut", "mcut", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mcuti$pack $ACC40Si,$s6,$FRintk */
  {
    FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mcutss$pack $ACC40Si,$FRintj,$FRintk */
  {
    FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mcutssi$pack $ACC40Si,$s6,$FRintk */
  {
    FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mdcutssi$pack $ACC40Si,$s6,$FRintk */
  {
    FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* maveh$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MAVEH, "maveh", "maveh", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* msllhi$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* msrlhi$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* msrahi$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mdrotli$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* mcplhi$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* mcpli$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* msaths$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MSATHS, "msaths", "msaths", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mqsaths$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* msathu$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MSATHU, "msathu", "msathu", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mcmpsh$pack $FRinti,$FRintj,$FCCk */
  {
    FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mcmpuh$pack $FRinti,$FRintj,$FCCk */
  {
    FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mabshs$pack $FRintj,$FRintk */
  {
    FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* maddhss$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* maddhus$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* msubhss$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* msubhus$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
  },
/* mqaddhss$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* mqaddhus$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* mqsubhss$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* mqsubhus$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
  },
/* maddaccs$pack $ACC40Si,$ACC40Sk */
  {
    FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* msubaccs$pack $ACC40Si,$ACC40Sk */
  {
    FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mdaddaccs$pack $ACC40Si,$ACC40Sk */
  {
    FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* mdsubaccs$pack $ACC40Si,$ACC40Sk */
  {
    FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* masaccs$pack $ACC40Si,$ACC40Sk */
  {
    FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
  },
/* mdasaccs$pack $ACC40Si,$ACC40Sk */
  {
    FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
  {
    FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
  {
    FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
  {
    FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */
  {
    FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
  {
    FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
  },
/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
  {
    FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
  },
/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
  {
    FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
  },
/* mexpdhw$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mexpdhd$pack $FRinti,$u6,$FRintk */
  {
    FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* mpackh$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mdpackh$pack $FRinti,$FRintj,$FRintk */
  {
    FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } }
  },
/* munpackh$pack $FRinti,$FRintk */
  {
    FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* mdunpackh$pack $FRinti,$FRintk */
  {
    FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
  },
/* mbtoh$pack $FRintj,$FRintk */
  {
    FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* mhtob$pack $FRintj,$FRintk */
  {
    FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
  },
/* mbtohe$pack $FRintj,$FRintk */
  {
    FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
  },
/* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
  {
    FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
  },
/* mclracc$pack $ACC40Sk,$A */
  {
    FRV_INSN_MCLRACC, "mclracc", "mclracc", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
  },
/* mrdacc$pack $ACC40Si,$FRintk */
  {
    FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mrdaccg$pack $ACCGi,$FRintk */
  {
    FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
  },
/* mwtacc$pack $FRinti,$ACC40Sk */
  {
    FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
  },
/* mwtaccg$pack $FRinti,$ACCGk */
  {
    FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
  },
/* mcop1$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
  },
/* mcop2$pack $FRi,$FRj,$FRk */
  {
    FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
  },
/* fnop$pack */
  {
    FRV_INSN_FNOP, "fnop", "fnop", 32,
    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } }
  },
};

#undef OP
#undef A

/* Initialize anything needed to be done once, before any cpu_open call.  */
static void init_tables PARAMS ((void));

static void
init_tables ()
{
}

static const CGEN_MACH * lookup_mach_via_bfd_name
  PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));

/* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name.  */

static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
     const CGEN_MACH *table;
     const char *name;
{
  while (table->name)
    {
      if (strcmp (name, table->bfd_name) == 0)
	return table;
      ++table;
    }
  abort ();
}

/* Subroutine of frv_cgen_cpu_open to build the hardware table.  */

static void
build_hw_table (cd)
     CGEN_CPU_TABLE *cd;
{
  int i;
  int machs = cd->machs;
  const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0];
  /* MAX_HW is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_HW_ENTRY **selected =
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));

  cd->hw_table.init_entries = init;
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
  /* ??? For now we just use machs to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
	& machs)
      selected[init[i].type] = &init[i];
  cd->hw_table.entries = selected;
  cd->hw_table.num_entries = MAX_HW;
}

/* Subroutine of frv_cgen_cpu_open to build the hardware table.  */

static void
build_ifield_table (cd)
     CGEN_CPU_TABLE *cd;
{
  cd->ifld_table = & frv_cgen_ifld_table[0];
}

/* Subroutine of frv_cgen_cpu_open to build the hardware table.  */

static void
build_operand_table (cd)
     CGEN_CPU_TABLE *cd;
{
  int i;
  int machs = cd->machs;
  const CGEN_OPERAND *init = & frv_cgen_operand_table[0];
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_OPERAND **selected =
    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));

  cd->operand_table.init_entries = init;
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
  /* ??? For now we just use mach to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
	& machs)
      selected[init[i].type] = &init[i];
  cd->operand_table.entries = selected;
  cd->operand_table.num_entries = MAX_OPERANDS;
}

/* Subroutine of frv_cgen_cpu_open to build the hardware table.
   ??? This could leave out insns not supported by the specified mach/isa,
   but that would cause errors like "foo only supported by bar" to become
   "unknown insn", so for now we include all insns and require the app to
   do the checking later.
   ??? On the other hand, parsing of such insns may require their hardware or
   operand elements to be in the table [which they mightn't be].  */

static void
build_insn_table (cd)
     CGEN_CPU_TABLE *cd;
{
  int i;
  const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));

  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
  for (i = 0; i < MAX_INSNS; ++i)
    insns[i].base = &ib[i];
  cd->insn_table.init_entries = insns;
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
  cd->insn_table.num_init_entries = MAX_INSNS;
}

/* Subroutine of frv_cgen_cpu_open to rebuild the tables.  */

static void
frv_cgen_rebuild_tables (cd)
     CGEN_CPU_TABLE *cd;
{
  int i;
  unsigned int isas = cd->isas;
  unsigned int machs = cd->machs;

  cd->int_insn_p = CGEN_INT_INSN_P;

  /* Data derived from the isa spec.  */
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
  cd->default_insn_bitsize = UNSET;
  cd->base_insn_bitsize = UNSET;
  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
  cd->max_insn_bitsize = 0;
  for (i = 0; i < MAX_ISAS; ++i)
    if (((1 << i) & isas) != 0)
      {
	const CGEN_ISA *isa = & frv_cgen_isa_table[i];

	/* Default insn sizes of all selected isas must be
	   equal or we set the result to 0, meaning "unknown".  */
	if (cd->default_insn_bitsize == UNSET)
	  cd->default_insn_bitsize = isa->default_insn_bitsize;
	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
	  ; /* this is ok */
	else
	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;

	/* Base insn sizes of all selected isas must be equal
	   or we set the result to 0, meaning "unknown".  */
	if (cd->base_insn_bitsize == UNSET)
	  cd->base_insn_bitsize = isa->base_insn_bitsize;
	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
	  ; /* this is ok */
	else
	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;

	/* Set min,max insn sizes.  */
	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
	  cd->min_insn_bitsize = isa->min_insn_bitsize;
	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
	  cd->max_insn_bitsize = isa->max_insn_bitsize;
      }

  /* Data derived from the mach spec.  */
  for (i = 0; i < MAX_MACHS; ++i)
    if (((1 << i) & machs) != 0)
      {
	const CGEN_MACH *mach = & frv_cgen_mach_table[i];

	if (mach->insn_chunk_bitsize != 0)
	{
	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
	    {
	      fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
	      abort ();
	    }

 	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
	}
      }

  /* Determine which hw elements are used by MACH.  */
  build_hw_table (cd);

  /* Build the ifield table.  */
  build_ifield_table (cd);

  /* Determine which operands are used by MACH/ISA.  */
  build_operand_table (cd);

  /* Build the instruction table.  */
  build_insn_table (cd);
}

/* Initialize a cpu table and return a descriptor.
   It's much like opening a file, and must be the first function called.
   The arguments are a set of (type/value) pairs, terminated with
   CGEN_CPU_OPEN_END.

   Currently supported values:
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
   CGEN_CPU_OPEN_END:     terminates arguments

   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
   precluded.

   ??? We only support ISO C stdargs here, not K&R.
   Laziness, plus experiment to see if anything requires K&R - eventually
   K&R will no longer be supported - e.g. GDB is currently trying this.  */

CGEN_CPU_DESC
frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
  static int init_p;
  unsigned int isas = 0;  /* 0 = "unspecified" */
  unsigned int machs = 0; /* 0 = "unspecified" */
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
  va_list ap;

  if (! init_p)
    {
      init_tables ();
      init_p = 1;
    }

  memset (cd, 0, sizeof (*cd));

  va_start (ap, arg_type);
  while (arg_type != CGEN_CPU_OPEN_END)
    {
      switch (arg_type)
	{
	case CGEN_CPU_OPEN_ISAS :
	  isas = va_arg (ap, unsigned int);
	  break;
	case CGEN_CPU_OPEN_MACHS :
	  machs = va_arg (ap, unsigned int);
	  break;
	case CGEN_CPU_OPEN_BFDMACH :
	  {
	    const char *name = va_arg (ap, const char *);
	    const CGEN_MACH *mach =
	      lookup_mach_via_bfd_name (frv_cgen_mach_table, name);

	    machs |= 1 << mach->num;
	    break;
	  }
	case CGEN_CPU_OPEN_ENDIAN :
	  endian = va_arg (ap, enum cgen_endian);
	  break;
	default :
	  fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
		   arg_type);
	  abort (); /* ??? return NULL? */
	}
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
    }
  va_end (ap);

  /* mach unspecified means "all" */
  if (machs == 0)
    machs = (1 << MAX_MACHS) - 1;
  /* base mach is always selected */
  machs |= 1;
  /* isa unspecified means "all" */
  if (isas == 0)
    isas = (1 << MAX_ISAS) - 1;
  if (endian == CGEN_ENDIAN_UNKNOWN)
    {
      /* ??? If target has only one, could have a default.  */
      fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
      abort ();
    }

  cd->isas = isas;
  cd->machs = machs;
  cd->endian = endian;
  /* FIXME: for the sparc case we can determine insn-endianness statically.
     The worry here is where both data and insn endian can be independently
     chosen, in which case this function will need another argument.
     Actually, will want to allow for more arguments in the future anyway.  */
  cd->insn_endian = endian;

  /* Table (re)builder.  */
  cd->rebuild_tables = frv_cgen_rebuild_tables;
  frv_cgen_rebuild_tables (cd);

  /* Default to not allowing signed overflow.  */
  cd->signed_overflow_ok_p = 0;
  
  return (CGEN_CPU_DESC) cd;
}

/* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
   MACH_NAME is the bfd name of the mach.  */

CGEN_CPU_DESC
frv_cgen_cpu_open_1 (mach_name, endian)
     const char *mach_name;
     enum cgen_endian endian;
{
  return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
			       CGEN_CPU_OPEN_ENDIAN, endian,
			       CGEN_CPU_OPEN_END);
}

/* Close a cpu table.
   ??? This can live in a machine independent file, but there's currently
   no place to put this file (there's no libcgen).  libopcodes is the wrong
   place as some simulator ports use this but they don't use libopcodes.  */

void
frv_cgen_cpu_close (cd)
     CGEN_CPU_DESC cd;
{
  unsigned int i;
  CGEN_INSN *insns;

  if (cd->macro_insn_table.init_entries)
    {
      insns = cd->macro_insn_table.init_entries;
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
	{
	  if (CGEN_INSN_RX ((insns)))
	    regfree(CGEN_INSN_RX (insns));
	}
    }

  if (cd->insn_table.init_entries)
    {
      insns = cd->insn_table.init_entries;
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
	{
	  if (CGEN_INSN_RX (insns))
	    regfree(CGEN_INSN_RX (insns));
	}
    }

  
  if (cd->macro_insn_table.init_entries)
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

  if (cd->insn_table.init_entries)
    free ((CGEN_INSN *) cd->insn_table.init_entries);

  if (cd->hw_table.entries)
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);

  if (cd->operand_table.entries)
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);

  free (cd);
}