)]}'
{
  "commit": "d30eb38d5b4e714153b0084bd8aff237f598fc9d",
  "tree": "8e615529979c0448a99b120b677f136106a3c040",
  "parents": [
    "2ec6065a4f3fe95d287602cb9158a7ce1fbed2e9"
  ],
  "author": {
    "name": "Victor Do Nascimento",
    "email": "victor.donascimento@arm.com",
    "time": "Wed Dec 13 14:09:08 2023 +0000"
  },
  "committer": {
    "name": "Victor Do Nascimento",
    "email": "victor.donascimento@arm.com",
    "time": "Tue Jan 09 10:16:40 2024 +0000"
  },
  "message": "aarch64: Add support for xzr register in register pair operands\n\nAnalysis of the allowed operand values for `sysp\u0027 and `tlbip\u0027 reveals\na significant departure from the allowed behavior for operand register\npairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other\ninsns in this category.\n\nFor instructions `casp\u0027, `mrrs\u0027 and `msrr\u0027 the register pair must\nalways start at an even index and the second register in the pair is\nthe index + 1.  This precludes the use of xzr as the first register,\ngiven it corresponds to register number 31.\n\nThis is different in the case of `sysp\u0027 and `tlbip\u0027, however.  These\nallow the use of xzr and, where the first operand in the pair is\nomitted, this is the default value assigned to it.  When this\noperand is assigned xzr, it is expected that the second operand will\nlikewise take on a value of xzr.\n\nThese two instructions therefore \"break\" two rules of register pairs:\n\n  * The first of the two registers is odd-numbered.\n  * The index of the second register is equal to that of the first,\n  and not n+1.\n\nTo allow for this departure from hitherto standard behavior, we\nextend the functionality of the assembler by defining an extension of\nthe AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR.\n\nIt is used in defining `sysp\u0027 and `tlbip\u0027 and allows\n`operand_general_constraint_met_p\u0027 to allow the pair to both take on\nthe value of xzr.\n",
  "tree_diff": [
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