)]}'
{
  "commit": "d39b60f2e036f4af7224adf06c2d70bb3f8f71f3",
  "tree": "ad8db1687a23ec30749888e39c20c58a469f871b",
  "parents": [
    "b8a175b415454df6a039ba0b5d2ff13c3c180275"
  ],
  "author": {
    "name": "John Baldwin",
    "email": "jhb@FreeBSD.org",
    "time": "Mon Aug 28 14:18:19 2023 -0700"
  },
  "committer": {
    "name": "John Baldwin",
    "email": "jhb@FreeBSD.org",
    "time": "Mon Aug 28 14:18:19 2023 -0700"
  },
  "message": "x86: Add an x86_xsave_layout structure to handle variable XSAVE layouts.\n\nThe standard layout of the XSAVE extended state area consists of three\nregions.  The first 512 bytes (legacy region) match the layout of the\nFXSAVE instruction including floating point registers, MMX registers,\nand SSE registers.  The next 64 bytes (XSAVE header) contains a header\nwith a fixed layout.  The final region (extended region) contains zero\nor more optional state components.  Examples of these include the\nupper 128 bits of YMM registers for AVX.\n\nThese optional state components generally have an\narchitecturally-fixed size, but they are not assigned architectural\noffsets in the extended region.  Instead, processors provide\nadditional CPUID leafs describing the size and offset of each\ncomponent in the \"standard\" layout for a given CPU.  (There is also a\n\"compact\" format which uses an alternate layout, but existing OS\u0027s\ncurrently export the \"standard\" layout when exporting XSAVE data via\nptrace() and core dumps.)\n\nTo date, GDB has assumed the layout used on current Intel processors\nfor state components in the extended region and hardcoded those\noffsets in the tables in i387-tdep.c and i387-fp.cc.  However, this\nfails on recent AMD processors which use a different layout.\nSpecifically, AMD Zen3 and later processors do not leave space for the\nMPX register set in between the AVX and AVX512 register sets.\n\nTo rectify this, add an x86_xsave_layout structure which contains the\ntotal size of the XSAVE extended state area as well as the offset of\neach known optional state component.\n\nSubsequent commits will modify XSAVE parsing in both gdb and gdbserver\nto use x86_xsave_layout.\n\nCo-authored-by: Aleksandar Paunovic \u003caleksandar.paunovic@intel.com\u003e\nApproved-By: Simon Marchi \u003csimon.marchi@efficios.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b8740fd87010c070ce19c89f9375ea4689fae35d",
      "old_mode": 33188,
      "old_path": "gdbsupport/x86-xstate.h",
      "new_id": "6ac1c39e21343bb4049199bcdebbe623fd0ce9e0",
      "new_mode": 33188,
      "new_path": "gdbsupport/x86-xstate.h"
    }
  ]
}