ARM assembler: Allow up to 32 single precision registers in the VPUSH and VPOP instructions.
PR 28436
* config/tc-arm.c (do_vfp_nsyn_push_pop_check): New function.
(do_vfp_nsyn_pop): Use the new function.
(do_vfp_nsyn_push): Use the new function.
* testsuite/gas/arm/v8_1m-mve.s: Add new instructions.
* testsuite/gas/arm/v8_1m-mve.d: Updated expected disassembly.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 25ad2d1..1133847 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2021-10-28 Markus Klein <markus.klein@sma.de>
+
+ PR 28436
+ * config/tc-arm.c (do_vfp_nsyn_push_pop_check): New function.
+ (do_vfp_nsyn_pop): Use the new function.
+ (do_vfp_nsyn_push): Use the new function.
+ * testsuite/gas/arm/v8_1m-mve.s: Add new instructions.
+ * testsuite/gas/arm/v8_1m-mve.d: Updated expected disassembly.
+
2021-09-27 Nick Alcock <nick.alcock@oracle.com>
* configure: Regenerate.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 302a18f..9ad7009 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -20737,19 +20737,31 @@
}
static void
+do_vfp_nsyn_push_pop_check (void)
+{
+ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd), _(BAD_FPU));
+
+ if (inst.operands[1].issingle)
+ {
+ constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 32,
+ _("register list must contain at least 1 and at most 32 registers"));
+ }
+ else
+ {
+ constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
+ _("register list must contain at least 1 and at most 16 registers"));
+ }
+}
+
+static void
do_vfp_nsyn_pop (void)
{
nsyn_insert_sp ();
- if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) {
+
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
return do_vfp_nsyn_opcode ("vldm");
- }
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
- _(BAD_FPU));
-
- constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
- _("register list must contain at least 1 and at most 16 "
- "registers"));
+ do_vfp_nsyn_push_pop_check ();
if (inst.operands[1].issingle)
do_vfp_nsyn_opcode ("fldmias");
@@ -20761,16 +20773,11 @@
do_vfp_nsyn_push (void)
{
nsyn_insert_sp ();
- if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) {
+
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
return do_vfp_nsyn_opcode ("vstmdb");
- }
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
- _(BAD_FPU));
-
- constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
- _("register list must contain at least 1 and at most 16 "
- "registers"));
+ do_vfp_nsyn_push_pop_check ();
if (inst.operands[1].issingle)
do_vfp_nsyn_opcode ("fstmdbs");
@@ -20778,7 +20785,6 @@
do_vfp_nsyn_opcode ("fstmdbd");
}
-
static void
do_neon_ldr_str (void)
{
diff --git a/gas/testsuite/gas/arm/v8_1m-mve.d b/gas/testsuite/gas/arm/v8_1m-mve.d
index 4c528de..a1eba2d 100644
--- a/gas/testsuite/gas/arm/v8_1m-mve.d
+++ b/gas/testsuite/gas/arm/v8_1m-mve.d
@@ -25,3 +25,7 @@
*[0-9a-f]+: ed91 fb00 vldr d15, \[r1\]
*[0-9a-f]+: edc1 fa00 vstr s31, \[r1\]
*[0-9a-f]+: edd1 fa00 vldr s31, \[r1\]
+ *[0-9a-f]+: ed2d 0a20 vpush {s0-s31}
+ *[0-9a-f]+: ed2d 0a10 vpush {s0-s15}
+ *[0-9a-f]+: ecbd 0a10 vpop {s0-s15}
+ *[0-9a-f]+: ecbd 0a20 vpop {s0-s31}
diff --git a/gas/testsuite/gas/arm/v8_1m-mve.s b/gas/testsuite/gas/arm/v8_1m-mve.s
index cae1f93..df34422 100644
--- a/gas/testsuite/gas/arm/v8_1m-mve.s
+++ b/gas/testsuite/gas/arm/v8_1m-mve.s
@@ -22,3 +22,8 @@
vldr d15,[r1]
vstr s31,[r1]
vldr s31,[r1]
+
+vpush {s0-s31} // -> false error, is a valid command
+vpush {s0-s15} // OK
+vpop {s0-s15} // OK
+vpop {s0-s31} // -> false error, is a valid command
