)]}'
{
  "commit": "db3c06bf93f577b9eb40e2cc5d67bfd0671d3c11",
  "tree": "d1cd2d63644a790b06a36afea900ccc5a509c302",
  "parents": [
    "56ead579a51f797beebc0d7745a613895383fe51"
  ],
  "author": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:07 2023 +0100"
  },
  "committer": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:07 2023 +0100"
  },
  "message": "aarch64: Add an operand class for SVE register lists\n\nSVE register lists were classified as SVE_REG, since there had been\nno particular reason to separate them out.  However, some SME2\ninstructions have tied register list operands, and so we need to\ndistinguish registers and register lists when checking whether two\noperands match.\n\nAlso, the register list operands used a general error message,\neven though we already have a dedicated error code for register\nlists that are the wrong length.\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
      "old_path": "gas/testsuite/gas/aarch64/illegal-sve2.l",
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      "new_mode": 33188,
      "new_path": "gas/testsuite/gas/aarch64/illegal-sve2.l"
    },
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      "old_mode": 33188,
      "old_path": "include/opcode/aarch64.h",
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      "new_mode": 33188,
      "new_path": "include/opcode/aarch64.h"
    },
    {
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      "old_path": "opcodes/aarch64-opc-2.c",
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      "new_mode": 33188,
      "new_path": "opcodes/aarch64-opc-2.c"
    },
    {
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      "new_path": "opcodes/aarch64-opc.c"
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    {
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      "new_path": "opcodes/aarch64-tbl.h"
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  ]
}