sim/Makefile.in

# Makefile.in generated by automake 1.15.1 from Makefile.am.
# @configure_input@

# Copyright (C) 1994-2017 Free Software Foundation, Inc.

# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.

# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.

@SET_MAKE@

#   Copyright (C) 1993-2024 Free Software Foundation, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.




VPATH = @srcdir@
am__is_gnu_make = { \
  if test -z '$(MAKELEVEL)'; then \
    false; \
  elif test -n '$(MAKE_HOST)'; then \
    true; \
  elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
    true; \
  else \
    false; \
  fi; \
}
am__make_running_with_option = \
  case $${target_option-} in \
      ?) ;; \
      *) echo "am__make_running_with_option: internal error: invalid" \
              "target option '$${target_option-}' specified" >&2; \
         exit 1;; \
  esac; \
  has_opt=no; \
  sane_makeflags=$$MAKEFLAGS; \
  if $(am__is_gnu_make); then \
    sane_makeflags=$$MFLAGS; \
  else \
    case $$MAKEFLAGS in \
      *\\[\ \	]*) \
        bs=\\; \
        sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
          | sed "s/$$bs$$bs[$$bs $$bs	]*//g"`;; \
    esac; \
  fi; \
  skip_next=no; \
  strip_trailopt () \
  { \
    flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
  }; \
  for flg in $$sane_makeflags; do \
    test $$skip_next = yes && { skip_next=no; continue; }; \
    case $$flg in \
      *=*|--*) continue;; \
        -*I) strip_trailopt 'I'; skip_next=yes;; \
      -*I?*) strip_trailopt 'I';; \
        -*O) strip_trailopt 'O'; skip_next=yes;; \
      -*O?*) strip_trailopt 'O';; \
        -*l) strip_trailopt 'l'; skip_next=yes;; \
      -*l?*) strip_trailopt 'l';; \
      -[dEDm]) skip_next=yes;; \
      -[JT]) skip_next=yes;; \
    esac; \
    case $$flg in \
      *$$target_option*) has_opt=yes; break;; \
    esac; \
  done; \
  test $$has_opt = yes
am__make_dryrun = (target_option=n; $(am__make_running_with_option))
am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
pkgdatadir = $(datadir)/@PACKAGE@
pkgincludedir = $(includedir)/@PACKAGE@
pkglibdir = $(libdir)/@PACKAGE@
pkglibexecdir = $(libexecdir)/@PACKAGE@
am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
install_sh_DATA = $(install_sh) -c -m 644
install_sh_PROGRAM = $(install_sh) -c
install_sh_SCRIPT = $(install_sh) -c
INSTALL_HEADER = $(INSTALL_DATA)
transform = $(program_transform_name)
NORMAL_INSTALL = :
PRE_INSTALL = :
POST_INSTALL = :
NORMAL_UNINSTALL = :
PRE_UNINSTALL = :
POST_UNINSTALL = :
build_triplet = @build@
host_triplet = @host@
target_triplet = @target@
check_PROGRAMS = $(am__EXEEXT_9) $(am__EXEEXT_10)
noinst_PROGRAMS = $(am__EXEEXT_11) $(am__EXEEXT_12) $(am__EXEEXT_13) \
	$(am__EXEEXT_14) $(am__EXEEXT_15) $(am__EXEEXT_16) \
	$(am__EXEEXT_17) $(am__EXEEXT_18) $(am__EXEEXT_19) \
	$(am__EXEEXT_20) $(am__EXEEXT_21) $(am__EXEEXT_22) \
	$(am__EXEEXT_23) $(am__EXEEXT_24) $(am__EXEEXT_25) \
	$(am__EXEEXT_26) $(am__EXEEXT_27) $(am__EXEEXT_28) \
	$(am__EXEEXT_29) $(am__EXEEXT_30) $(am__EXEEXT_31) \
	$(am__EXEEXT_32) $(am__EXEEXT_33) $(am__EXEEXT_34) \
	$(am__EXEEXT_35) $(am__EXEEXT_36) $(am__EXEEXT_37) \
	$(am__EXEEXT_38) $(am__EXEEXT_39) $(am__EXEEXT_40) \
	$(am__EXEEXT_41) $(am__EXEEXT_42)
EXTRA_PROGRAMS = $(am__EXEEXT_1) testsuite/common/bits-gen$(EXEEXT) \
	testsuite/common/fpu-tst$(EXEEXT) $(am__EXEEXT_2) \
	$(am__EXEEXT_3) $(am__EXEEXT_4) $(am__EXEEXT_5) \
	$(am__EXEEXT_7) $(am__EXEEXT_8)
@ENABLE_SIM_TRUE@am__append_1 = \
@ENABLE_SIM_TRUE@	$(srcroot)/include/sim/callback.h \
@ENABLE_SIM_TRUE@	$(srcroot)/include/sim/sim.h

@SIM_ENABLE_HW_TRUE@am__append_2 = \
@SIM_ENABLE_HW_TRUE@	$(SIM_COMMON_HW_OBJS) \
@SIM_ENABLE_HW_TRUE@	$(SIM_HW_SOCKSER)

TESTS = testsuite/common/bits32m0$(EXEEXT) \
	testsuite/common/bits32m31$(EXEEXT) \
	testsuite/common/bits64m0$(EXEEXT) \
	testsuite/common/bits64m63$(EXEEXT) \
	testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_3 = aarch64/libsim.a
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_4 = aarch64/run
@SIM_ENABLE_ARCH_arm_TRUE@am__append_5 = arm/libsim.a
@SIM_ENABLE_ARCH_arm_TRUE@am__append_6 = arm/run
@SIM_ENABLE_ARCH_avr_TRUE@am__append_7 = avr/libsim.a
@SIM_ENABLE_ARCH_avr_TRUE@am__append_8 = avr/run
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_9 = bfin/libsim.a
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_10 = bfin/run
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_11 = bpf/libsim.a
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_12 = bpf/run
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_13 = cr16/libsim.a
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/run
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/gencode
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/libsim.a
@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/run
@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/rvdummy
@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/engv32.h

@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/engv10.h cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/libsim.a
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/run
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 = $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = erc32/libsim.a
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = erc32/run erc32/sis
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 = sim-%D-install-exec-local
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 = sim-erc32-uninstall-local
@SIM_ENABLE_ARCH_examples_TRUE@am__append_35 = example-synacor/libsim.a
@SIM_ENABLE_ARCH_examples_TRUE@am__append_36 = example-synacor/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/libsim.a
@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_42 = ft32/libsim.a
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 = ft32/run
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_44 = h8300/libsim.a
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 = h8300/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/libsim.a
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_49 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = lm32/libsim.a
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = lm32/run
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 = $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/libsim.a
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = m32c/run
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 = m32c/opc2c
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_59 = \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.c.log

@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = m32r/libsim.a
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = m32r/run
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng2.h

@SIM_ENABLE_ARCH_m32r_TRUE@am__append_63 = m32r/eng.h m32r/engx.h m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 = $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/libsim.a
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = m68hc11/run
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_67 = m68hc11/gencode
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_68 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_69 = mcore/libsim.a
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_70 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_71 = microblaze/libsim.a
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_72 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_73 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/icache.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/engine.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/irun.o

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_74 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_icache.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	\
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_icache.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	\
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16run.o

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_75 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	$(SIM_MIPS_MULTI_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/multi-run.o

@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/libsim.a
@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@	$(SIM_MIPS_MULTI_SRC)
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_79 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/stamp-gen-mode-single

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_80 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mode-m16-m32

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_81 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	$(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-mode-multi-run

@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = mn10300/libsim.a
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/model.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.h

@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_88 = moxie/libsim.a
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_89 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_90 = msp430/libsim.a
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/libsim.a
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/libsim.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/run
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/defines.h ppc/icache.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/idecode.h ppc/semantics.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/model.h ppc/support.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/itable.h ppc/hw.h
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = ppc/defines.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/stamp-defines \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(ppc_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(ppc_IGEN_TOOLS) ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_101 = ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_102 = $(ppc_IGEN_TOOLS)
@SIM_ENABLE_ARCH_pru_TRUE@am__append_103 = pru/libsim.a
@SIM_ENABLE_ARCH_pru_TRUE@am__append_104 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_105 = riscv/libsim.a
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_106 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_107 = rl78/libsim.a
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_108 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_109 = rx/libsim.a
@SIM_ENABLE_ARCH_rx_TRUE@am__append_110 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = sh/libsim.a
@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/ppi.c

@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = v850/libsim.a
@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_118 = \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/model.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.h

@SIM_ENABLE_ARCH_v850_TRUE@am__append_119 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
	$(top_srcdir)/../config/depstand.m4 \
	$(top_srcdir)/../config/lead-dot.m4 \
	$(top_srcdir)/../config/override.m4 \
	$(top_srcdir)/../config/pkg.m4 $(top_srcdir)/../libtool.m4 \
	$(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \
	$(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \
	$(top_srcdir)/m4/sim_ac_option_alignment.m4 \
	$(top_srcdir)/m4/sim_ac_option_assert.m4 \
	$(top_srcdir)/m4/sim_ac_option_cgen_maint.m4 \
	$(top_srcdir)/m4/sim_ac_option_debug.m4 \
	$(top_srcdir)/m4/sim_ac_option_endian.m4 \
	$(top_srcdir)/m4/sim_ac_option_environment.m4 \
	$(top_srcdir)/m4/sim_ac_option_hardware.m4 \
	$(top_srcdir)/m4/sim_ac_option_inline.m4 \
	$(top_srcdir)/m4/sim_ac_option_profile.m4 \
	$(top_srcdir)/m4/sim_ac_option_reserved_bits.m4 \
	$(top_srcdir)/m4/sim_ac_option_scache.m4 \
	$(top_srcdir)/m4/sim_ac_option_smp.m4 \
	$(top_srcdir)/m4/sim_ac_option_stdio.m4 \
	$(top_srcdir)/m4/sim_ac_option_trace.m4 \
	$(top_srcdir)/m4/sim_ac_option_warnings.m4 \
	$(top_srcdir)/m4/sim_ac_platform.m4 \
	$(top_srcdir)/m4/sim_ac_toolchain.m4 \
	$(top_srcdir)/../gdbsupport/libiberty.m4 \
	$(top_srcdir)/frv/acinclude.m4 $(top_srcdir)/mips/acinclude.m4 \
	$(top_srcdir)/ppc/acinclude.m4 \
	$(top_srcdir)/riscv/acinclude.m4 $(top_srcdir)/rx/acinclude.m4 \
	$(top_srcdir)/configure.ac
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
	$(ACLOCAL_M4)
DIST_COMMON = $(srcdir)/Makefile.am $(top_srcdir)/configure \
	$(am__configure_deps) $(am__pkginclude_HEADERS_DIST)
am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
 configure.lineno config.status.lineno
mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
CONFIG_HEADER = config.h
CONFIG_CLEAN_FILES = aarch64/.gdbinit arm/.gdbinit avr/.gdbinit \
	bfin/.gdbinit bpf/.gdbinit cr16/.gdbinit cris/.gdbinit \
	d10v/.gdbinit frv/.gdbinit ft32/.gdbinit h8300/.gdbinit \
	iq2000/.gdbinit lm32/.gdbinit m32c/.gdbinit m32r/.gdbinit \
	m68hc11/.gdbinit mcore/.gdbinit microblaze/.gdbinit \
	mips/.gdbinit mn10300/.gdbinit moxie/.gdbinit msp430/.gdbinit \
	or1k/.gdbinit ppc/.gdbinit pru/.gdbinit riscv/.gdbinit \
	rl78/.gdbinit rx/.gdbinit sh/.gdbinit erc32/.gdbinit \
	v850/.gdbinit example-synacor/.gdbinit .gdbinit
CONFIG_CLEAN_VPATH_FILES =
LIBRARIES = $(noinst_LIBRARIES)
ARFLAGS = cru
AM_V_AR = $(am__v_AR_@AM_V@)
am__v_AR_ = $(am__v_AR_@AM_DEFAULT_V@)
am__v_AR_0 = @echo "  AR      " $@;
am__v_AR_1 = 
aarch64_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_aarch64_TRUE@	%,aarch64/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_aarch64_TRUE@	%,aarch64/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/cpustate.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/interp.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/memory.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/sim-resume.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/simulator.o
am__dirstamp = $(am__leading_dot)dirstamp
am__objects_1 = common/callback.$(OBJEXT) common/portability.$(OBJEXT) \
	common/sim-load.$(OBJEXT) common/sim-signal.$(OBJEXT) \
	common/syscall.$(OBJEXT) common/target-newlib-errno.$(OBJEXT) \
	common/target-newlib-open.$(OBJEXT) \
	common/target-newlib-signal.$(OBJEXT) \
	common/target-newlib-syscall.$(OBJEXT) \
	common/version.$(OBJEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am_aarch64_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_aarch64_TRUE@nodist_aarch64_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/modules.$(OBJEXT)
aarch64_libsim_a_OBJECTS = $(am_aarch64_libsim_a_OBJECTS) \
	$(nodist_aarch64_libsim_a_OBJECTS)
arm_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_DEPENDENCIES = arm/wrapper.o \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_arm_TRUE@	%,arm/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_arm_TRUE@	%,arm/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armemu.o arm/armemu32.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/arminit.o arm/armos.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armsupp.o arm/armvirt.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/thumbemu.o arm/armcopro.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/maverick.o arm/iwmmxt.o
@SIM_ENABLE_ARCH_arm_TRUE@am_arm_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/modules.$(OBJEXT)
arm_libsim_a_OBJECTS = $(am_arm_libsim_a_OBJECTS) \
	$(nodist_arm_libsim_a_OBJECTS)
avr_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_DEPENDENCIES = avr/interp.o \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_avr_TRUE@	%,avr/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_avr_TRUE@	%,avr/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/sim-resume.o
@SIM_ENABLE_ARCH_avr_TRUE@am_avr_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_avr_TRUE@nodist_avr_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/modules.$(OBJEXT)
avr_libsim_a_OBJECTS = $(am_avr_libsim_a_OBJECTS) \
	$(nodist_avr_libsim_a_OBJECTS)
bfin_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_bfin_TRUE@	%,bfin/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_bfin_TRUE@	%,bfin/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_bfin_TRUE@	%,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/bfin-sim.o bfin/devices.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/gui.o bfin/interp.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/machs.o bfin/sim-resume.o
@SIM_ENABLE_ARCH_bfin_TRUE@am_bfin_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_bfin_TRUE@nodist_bfin_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/modules.$(OBJEXT)
bfin_libsim_a_OBJECTS = $(am_bfin_libsim_a_OBJECTS) \
	$(nodist_bfin_libsim_a_OBJECTS)
bpf_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = bpf/bpf-sim.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@	%,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@	%,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/sim-resume.o
@SIM_ENABLE_ARCH_bpf_TRUE@am_bpf_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/modules.$(OBJEXT)
bpf_libsim_a_OBJECTS = $(am_bpf_libsim_a_OBJECTS) \
	$(nodist_bpf_libsim_a_OBJECTS)
common_libcommon_a_AR = $(AR) $(ARFLAGS)
common_libcommon_a_LIBADD =
am_common_libcommon_a_OBJECTS = common/callback.$(OBJEXT) \
	common/portability.$(OBJEXT) common/sim-load.$(OBJEXT) \
	common/sim-signal.$(OBJEXT) common/syscall.$(OBJEXT) \
	common/target-newlib-errno.$(OBJEXT) \
	common/target-newlib-open.$(OBJEXT) \
	common/target-newlib-signal.$(OBJEXT) \
	common/target-newlib-syscall.$(OBJEXT) \
	common/version.$(OBJEXT)
common_libcommon_a_OBJECTS = $(am_common_libcommon_a_OBJECTS)
cr16_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_cr16_TRUE@	%,cr16/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cr16_TRUE@	%,cr16/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/interp.o cr16/sim-resume.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/simops.o cr16/table.o
@SIM_ENABLE_ARCH_cr16_TRUE@am_cr16_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/modules.$(OBJEXT)
cr16_libsim_a_OBJECTS = $(am_cr16_libsim_a_OBJECTS) \
	$(nodist_cr16_libsim_a_OBJECTS)
cris_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_cris_TRUE@	%,cris/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cris_TRUE@	%,cris/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cris_TRUE@	%,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-run.o cris/cgen-scache.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-trace.o cris/cgen-utils.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/arch.o cris/crisv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cpuv10.o cris/decodev10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modelv10.o cris/mloopv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/crisv32f.o cris/cpuv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/decodev32.o cris/modelv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv32f.o cris/sim-if.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/traps.o
@SIM_ENABLE_ARCH_cris_TRUE@am_cris_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_cris_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modules.$(OBJEXT)
cris_libsim_a_OBJECTS = $(am_cris_libsim_a_OBJECTS) \
	$(nodist_cris_libsim_a_OBJECTS)
d10v_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_DEPENDENCIES = d10v/interp.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_d10v_TRUE@	%,d10v/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_d10v_TRUE@	%,d10v/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/endian.o d10v/sim-resume.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/simops.o d10v/table.o
@SIM_ENABLE_ARCH_d10v_TRUE@am_d10v_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_d10v_TRUE@nodist_d10v_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/modules.$(OBJEXT)
d10v_libsim_a_OBJECTS = $(am_d10v_libsim_a_OBJECTS) \
	$(nodist_d10v_libsim_a_OBJECTS)
erc32_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/erc32.o erc32/exec.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/float.o erc32/func.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/help.o erc32/interf.o
@SIM_ENABLE_ARCH_erc32_TRUE@am_erc32_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_erc32_TRUE@nodist_erc32_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/modules.$(OBJEXT)
erc32_libsim_a_OBJECTS = $(am_erc32_libsim_a_OBJECTS) \
	$(nodist_erc32_libsim_a_OBJECTS)
example_synacor_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_examples_TRUE@	%,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_examples_TRUE@	%,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/interp.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-main.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-resume.o
@SIM_ENABLE_ARCH_examples_TRUE@am_example_synacor_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_examples_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_examples_TRUE@nodist_example_synacor_libsim_a_OBJECTS = example-synacor/modules.$(OBJEXT)
example_synacor_libsim_a_OBJECTS =  \
	$(am_example_synacor_libsim_a_OBJECTS) \
	$(nodist_example_synacor_libsim_a_OBJECTS)
frv_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_frv_TRUE@	%,frv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_frv_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_frv_TRUE@	%,frv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-accfp.o frv/cgen-fpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-run.o frv/cgen-scache.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-trace.o frv/cgen-utils.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/arch.o frv/cgen-par.o frv/cpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/decode.o frv/frv.o frv/mloop.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/model.o frv/sem.o frv/cache.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/interrupts.o frv/memory.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/options.o frv/pipeline.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile.o frv/profile-fr400.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr450.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr500.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr550.o frv/registers.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/reset.o frv/sim-if.o frv/traps.o
@SIM_ENABLE_ARCH_frv_TRUE@am_frv_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_frv_TRUE@nodist_frv_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/modules.$(OBJEXT)
frv_libsim_a_OBJECTS = $(am_frv_libsim_a_OBJECTS) \
	$(nodist_frv_libsim_a_OBJECTS)
ft32_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_ft32_TRUE@	%,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_ft32_TRUE@	%,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/interp.o ft32/sim-resume.o
@SIM_ENABLE_ARCH_ft32_TRUE@am_ft32_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_ft32_TRUE@nodist_ft32_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/modules.$(OBJEXT)
ft32_libsim_a_OBJECTS = $(am_ft32_libsim_a_OBJECTS) \
	$(nodist_ft32_libsim_a_OBJECTS)
h8300_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/compile.o $(patsubst \
@SIM_ENABLE_ARCH_h8300_TRUE@	%,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_h8300_TRUE@	%,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/sim-resume.o
@SIM_ENABLE_ARCH_h8300_TRUE@am_h8300_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_h8300_TRUE@nodist_h8300_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/modules.$(OBJEXT)
h8300_libsim_a_OBJECTS = $(am_h8300_libsim_a_OBJECTS) \
	$(nodist_h8300_libsim_a_OBJECTS)
igen_libigen_a_AR = $(AR) $(ARFLAGS)
igen_libigen_a_LIBADD =
am_igen_libigen_a_OBJECTS = igen/table.$(OBJEXT) igen/lf.$(OBJEXT) \
	igen/misc.$(OBJEXT) igen/filter_host.$(OBJEXT) \
	igen/ld-decode.$(OBJEXT) igen/ld-cache.$(OBJEXT) \
	igen/filter.$(OBJEXT) igen/ld-insn.$(OBJEXT) \
	igen/gen-model.$(OBJEXT) igen/gen-itable.$(OBJEXT) \
	igen/gen-icache.$(OBJEXT) igen/gen-semantics.$(OBJEXT) \
	igen/gen-idecode.$(OBJEXT) igen/gen-support.$(OBJEXT) \
	igen/gen-engine.$(OBJEXT) igen/gen.$(OBJEXT)
igen_libigen_a_OBJECTS = $(am_igen_libigen_a_OBJECTS)
iq2000_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_iq2000_TRUE@	%,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_iq2000_TRUE@	%,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-run.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-scache.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-trace.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-utils.o iq2000/arch.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cpu.o iq2000/decode.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/iq2000.o iq2000/sem.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/mloop.o iq2000/model.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/sim-if.o
@SIM_ENABLE_ARCH_iq2000_TRUE@am_iq2000_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_iq2000_TRUE@nodist_iq2000_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/modules.$(OBJEXT)
iq2000_libsim_a_OBJECTS = $(am_iq2000_libsim_a_OBJECTS) \
	$(nodist_iq2000_libsim_a_OBJECTS)
lm32_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_lm32_TRUE@	%,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_lm32_TRUE@	%,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_lm32_TRUE@	%,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-run.o lm32/cgen-scache.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-trace.o lm32/cgen-utils.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/arch.o lm32/cpu.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/decode.o lm32/sem.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/mloop.o lm32/model.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/lm32.o lm32/sim-if.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/traps.o lm32/user.o
@SIM_ENABLE_ARCH_lm32_TRUE@am_lm32_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_lm32_TRUE@nodist_lm32_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/modules.$(OBJEXT)
lm32_libsim_a_OBJECTS = $(am_lm32_libsim_a_OBJECTS) \
	$(nodist_lm32_libsim_a_OBJECTS)
m32c_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_DEPENDENCIES = m32c/gdb-if.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/int.o m32c/load.o m32c/m32c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/mem.o m32c/misc.o m32c/r8c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/reg.o m32c/srcdest.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/syscalls.o m32c/trace.o
@SIM_ENABLE_ARCH_m32c_TRUE@am_m32c_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_m32c_TRUE@nodist_m32c_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/modules.$(OBJEXT)
m32c_libsim_a_OBJECTS = $(am_m32c_libsim_a_OBJECTS) \
	$(nodist_m32c_libsim_a_OBJECTS)
m32r_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_m32r_TRUE@	%,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m32r_TRUE@	%,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m32r_TRUE@	%,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-run.o m32r/cgen-scache.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-trace.o m32r/cgen-utils.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/arch.o m32r/m32r.o m32r/cpu.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decode.o m32r/sem.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model.o m32r/mloop.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32rx.o m32r/cpux.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decodex.o m32r/modelx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloopx.o m32r/m32r2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpu2.o m32r/decode2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model2.o m32r/mloop2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/sim-if.o m32r/traps.o
@SIM_ENABLE_ARCH_m32r_TRUE@am_m32r_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/modules.$(OBJEXT)
m32r_libsim_a_OBJECTS = $(am_m32r_libsim_a_OBJECTS) \
	$(nodist_m32r_libsim_a_OBJECTS)
m68hc11_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interp.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc12int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/emulos.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interrupts.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11_sim.o $(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	%,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	%,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	%,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/sim-resume.o
@SIM_ENABLE_ARCH_m68hc11_TRUE@am_m68hc11_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_m68hc11_TRUE@nodist_m68hc11_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/modules.$(OBJEXT)
m68hc11_libsim_a_OBJECTS = $(am_m68hc11_libsim_a_OBJECTS) \
	$(nodist_m68hc11_libsim_a_OBJECTS)
mcore_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/interp.o $(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@	%,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@	%,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/sim-resume.o
@SIM_ENABLE_ARCH_mcore_TRUE@am_mcore_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_mcore_TRUE@nodist_mcore_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/modules.$(OBJEXT)
mcore_libsim_a_OBJECTS = $(am_mcore_libsim_a_OBJECTS) \
	$(nodist_mcore_libsim_a_OBJECTS)
microblaze_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/interp.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_microblaze_TRUE@	%,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_microblaze_TRUE@	%,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/sim-resume.o
@SIM_ENABLE_ARCH_microblaze_TRUE@am_microblaze_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_microblaze_TRUE@nodist_microblaze_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/modules.$(OBJEXT)
microblaze_libsim_a_OBJECTS = $(am_microblaze_libsim_a_OBJECTS) \
	$(nodist_microblaze_libsim_a_OBJECTS)
mips_libsim_a_AR = $(AR) $(ARFLAGS)
am__DEPENDENCIES_1 =
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/multi-run.o
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_74) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__DEPENDENCIES_3) $(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@	%,mips/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@	%,mips/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@	%,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/cp1.o mips/dsp.o mips/mdmx.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sim-main.o mips/sim-resume.o
@SIM_ENABLE_ARCH_mips_TRUE@am_mips_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/modules.$(OBJEXT)
mips_libsim_a_OBJECTS = $(am_mips_libsim_a_OBJECTS) \
	$(nodist_mips_libsim_a_OBJECTS)
mn10300_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.o mn10300/irun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.o $(patsubst \
@SIM_ENABLE_ARCH_mn10300_TRUE@	%,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mn10300_TRUE@	%,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mn10300_TRUE@	%,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/interp.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/op_utils.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/sim-resume.o
@SIM_ENABLE_ARCH_mn10300_TRUE@am_mn10300_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_mn10300_TRUE@nodist_mn10300_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/modules.$(OBJEXT)
mn10300_libsim_a_OBJECTS = $(am_mn10300_libsim_a_OBJECTS) \
	$(nodist_mn10300_libsim_a_OBJECTS)
moxie_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_moxie_TRUE@	%,moxie/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_moxie_TRUE@	%,moxie/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/interp.o moxie/sim-resume.o
@SIM_ENABLE_ARCH_moxie_TRUE@am_moxie_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_moxie_TRUE@nodist_moxie_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/modules.$(OBJEXT)
moxie_libsim_a_OBJECTS = $(am_moxie_libsim_a_OBJECTS) \
	$(nodist_moxie_libsim_a_OBJECTS)
msp430_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_msp430_TRUE@	%,msp430/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_msp430_TRUE@	%,msp430/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/msp430-sim.o \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/sim-resume.o
@SIM_ENABLE_ARCH_msp430_TRUE@am_msp430_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_msp430_TRUE@nodist_msp430_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/modules.$(OBJEXT)
msp430_libsim_a_OBJECTS = $(am_msp430_libsim_a_OBJECTS) \
	$(nodist_msp430_libsim_a_OBJECTS)
or1k_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_or1k_TRUE@	%,or1k/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_or1k_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_or1k_TRUE@	%,or1k/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-accfp.o or1k/cgen-fpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-run.o or1k/cgen-scache.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-trace.o or1k/cgen-utils.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/arch.o or1k/cpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/decode.o or1k/mloop.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/model.o or1k/sem.o or1k/or1k.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/sim-if.o or1k/traps.o
@SIM_ENABLE_ARCH_or1k_TRUE@am_or1k_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_or1k_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_or1k_TRUE@nodist_or1k_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/modules.$(OBJEXT)
or1k_libsim_a_OBJECTS = $(am_or1k_libsim_a_OBJECTS) \
	$(nodist_or1k_libsim_a_OBJECTS)
ppc_libigen_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_DEPENDENCIES = igen/filter.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	igen/filter_host.o igen/lf.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	igen/misc.o
@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libigen_a_OBJECTS =  \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/table.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/lf-ppc.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/dumpf.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-decode.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-cache.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/filter-ppc.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-insn.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-model.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-itable.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-icache.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-semantics.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-idecode.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-support.$(OBJEXT)
ppc_libigen_a_OBJECTS = $(am_ppc_libigen_a_OBJECTS)
ppc_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_DEPENDENCIES = ppc/debug.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/bits.o ppc/sim-endian.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/os_emul.o ppc/emul_generic.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/emul_bugapi.o ppc/emul_chirp.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/emul_netbsd.o ppc/emul_unix.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/registers.o ppc/vm.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/corefile.o ppc/model.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/spreg.o ppc/cpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/interrupts.o ppc/events.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/cap.o ppc/device.o ppc/tree.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/device_table.o ppc/itable.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/mon.o ppc/icache.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/semantics.o ppc/idecode.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/support.o ppc/sim-fpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/psim.o ppc/pk_disklabel.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_ppc_TRUE@	%,ppc/%,$(sim_ppc_hw_obj)) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/options.o ppc/gdb-sim.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/sim_calls.o
@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libsim_a_OBJECTS = $(am__objects_1)
ppc_libsim_a_OBJECTS = $(am_ppc_libsim_a_OBJECTS)
pru_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_pru_TRUE@	%,pru/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_pru_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_pru_TRUE@	%,pru/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/interp.o pru/sim-resume.o
@SIM_ENABLE_ARCH_pru_TRUE@am_pru_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_pru_TRUE@nodist_pru_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/modules.$(OBJEXT)
pru_libsim_a_OBJECTS = $(am_pru_libsim_a_OBJECTS) \
	$(nodist_pru_libsim_a_OBJECTS)
riscv_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_riscv_TRUE@	%,riscv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_riscv_TRUE@	%,riscv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/interp.o riscv/machs.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/sim-main.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/sim-resume.o
@SIM_ENABLE_ARCH_riscv_TRUE@am_riscv_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_riscv_TRUE@nodist_riscv_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/modules.$(OBJEXT)
riscv_libsim_a_OBJECTS = $(am_riscv_libsim_a_OBJECTS) \
	$(nodist_riscv_libsim_a_OBJECTS)
rl78_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_DEPENDENCIES = rl78/load.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/mem.o rl78/cpu.o rl78/rl78.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/gdb-if.o rl78/trace.o
@SIM_ENABLE_ARCH_rl78_TRUE@am_rl78_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_rl78_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_rl78_TRUE@nodist_rl78_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/modules.$(OBJEXT)
rl78_libsim_a_OBJECTS = $(am_rl78_libsim_a_OBJECTS) \
	$(nodist_rl78_libsim_a_OBJECTS)
rx_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_DEPENDENCIES = rx/fpu.o rx/load.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/mem.o rx/misc.o rx/reg.o rx/rx.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/syscalls.o rx/trace.o rx/gdb-if.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/err.o
@SIM_ENABLE_ARCH_rx_TRUE@am_rx_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_rx_TRUE@nodist_rx_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/modules.$(OBJEXT)
rx_libsim_a_OBJECTS = $(am_rx_libsim_a_OBJECTS) \
	$(nodist_rx_libsim_a_OBJECTS)
sh_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_DEPENDENCIES = sh/interp.o \
@SIM_ENABLE_ARCH_sh_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_sh_TRUE@	%,sh/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_sh_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_sh_TRUE@	%,sh/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/table.o
@SIM_ENABLE_ARCH_sh_TRUE@am_sh_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_sh_TRUE@nodist_sh_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/modules.$(OBJEXT)
sh_libsim_a_OBJECTS = $(am_sh_libsim_a_OBJECTS) \
	$(nodist_sh_libsim_a_OBJECTS)
v850_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_v850_TRUE@	%,v850/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_v850_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_v850_TRUE@	%,v850/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/simops.o v850/interp.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.o v850/semantics.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.o v850/icache.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.o v850/irun.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.o v850/sim-resume.o
@SIM_ENABLE_ARCH_v850_TRUE@am_v850_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_v850_TRUE@	$(am__objects_1)
@SIM_ENABLE_ARCH_v850_TRUE@nodist_v850_libsim_a_OBJECTS =  \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/modules.$(OBJEXT)
v850_libsim_a_OBJECTS = $(am_v850_libsim_a_OBJECTS) \
	$(nodist_v850_libsim_a_OBJECTS)
am__EXEEXT_1 = $(IGEN) igen/filter$(EXEEXT) igen/gen$(EXEEXT) \
	igen/ld-cache$(EXEEXT) igen/ld-decode$(EXEEXT) \
	igen/ld-insn$(EXEEXT) igen/table$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_2 = cr16/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_3 = d10v/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_4 = m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_5 = m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_6 = $(PPC_IGEN) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-cache$(EXEEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-decode$(EXEEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-insn$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_7 = $(am__EXEEXT_6)
@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_8 = sh/gencode$(EXEEXT)
am__EXEEXT_9 = testsuite/common/bits32m0$(EXEEXT) \
	testsuite/common/bits32m31$(EXEEXT) \
	testsuite/common/bits64m0$(EXEEXT) \
	testsuite/common/bits64m63$(EXEEXT) \
	testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_10 = cris/rvdummy$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_11 = aarch64/run$(EXEEXT)
@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_12 = arm/run$(EXEEXT)
@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_13 = avr/run$(EXEEXT)
@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_14 = bfin/run$(EXEEXT)
@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_15 = bpf/run$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_16 = cr16/run$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_17 = cris/run$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_18 = d10v/run$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_19 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/sis$(EXEEXT)
@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_20 =  \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/run$(EXEEXT)
@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_21 = frv/run$(EXEEXT)
@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_22 = ft32/run$(EXEEXT)
@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_23 = h8300/run$(EXEEXT)
@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_24 = iq2000/run$(EXEEXT)
@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_25 = lm32/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_26 = m32c/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_27 = m32r/run$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_28 = m68hc11/run$(EXEEXT)
@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_29 = mcore/run$(EXEEXT)
@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_30 =  \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/run$(EXEEXT)
@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_31 = mips/run$(EXEEXT)
@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_32 = mn10300/run$(EXEEXT)
@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_33 = moxie/run$(EXEEXT)
@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_34 = msp430/run$(EXEEXT)
@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_35 = or1k/run$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_36 = ppc/run$(EXEEXT)
@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_37 = pru/run$(EXEEXT)
@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_38 = riscv/run$(EXEEXT)
@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_39 = rl78/run$(EXEEXT)
@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_40 = rx/run$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_41 = sh/run$(EXEEXT)
@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_42 = v850/run$(EXEEXT)
PROGRAMS = $(noinst_PROGRAMS)
am_aarch64_run_OBJECTS =
aarch64_run_OBJECTS = $(am_aarch64_run_OBJECTS)
am__DEPENDENCIES_4 = $(BFD_LIB) $(OPCODES_LIB) $(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/nrun.o aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(am__DEPENDENCIES_4)
AM_V_lt = $(am__v_lt_@AM_V@)
am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
am__v_lt_0 = --silent
am__v_lt_1 = 
am_arm_run_OBJECTS =
arm_run_OBJECTS = $(am_arm_run_OBJECTS)
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_DEPENDENCIES = arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/libsim.a $(am__DEPENDENCIES_4)
am_avr_run_OBJECTS =
avr_run_OBJECTS = $(am_avr_run_OBJECTS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_DEPENDENCIES = avr/nrun.o \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/libsim.a $(am__DEPENDENCIES_4)
am_bfin_run_OBJECTS =
bfin_run_OBJECTS = $(am_bfin_run_OBJECTS)
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_DEPENDENCIES = bfin/nrun.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/libsim.a $(am__DEPENDENCIES_4)
am_bpf_run_OBJECTS =
bpf_run_OBJECTS = $(am_bpf_run_OBJECTS)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_DEPENDENCIES = bpf/nrun.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_cr16_TRUE@am_cr16_gencode_OBJECTS =  \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/gencode.$(OBJEXT)
cr16_gencode_OBJECTS = $(am_cr16_gencode_OBJECTS)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/cr16-opc.o
am_cr16_run_OBJECTS =
cr16_run_OBJECTS = $(am_cr16_run_OBJECTS)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_DEPENDENCIES = cr16/nrun.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/libsim.a $(am__DEPENDENCIES_4)
am_cris_run_OBJECTS =
cris_run_OBJECTS = $(am_cris_run_OBJECTS)
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_DEPENDENCIES = cris/nrun.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_cris_TRUE@am_cris_rvdummy_OBJECTS =  \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/rvdummy.$(OBJEXT)
cris_rvdummy_OBJECTS = $(am_cris_rvdummy_OBJECTS)
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_cris_TRUE@	$(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_d10v_TRUE@am_d10v_gencode_OBJECTS =  \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/gencode.$(OBJEXT)
d10v_gencode_OBJECTS = $(am_d10v_gencode_OBJECTS)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/d10v-opc.o
am_d10v_run_OBJECTS =
d10v_run_OBJECTS = $(am_d10v_run_OBJECTS)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_DEPENDENCIES = d10v/nrun.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/libsim.a $(am__DEPENDENCIES_4)
am_erc32_run_OBJECTS =
erc32_run_OBJECTS = $(am_erc32_run_OBJECTS)
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_DEPENDENCIES = erc32/sis.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/libsim.a \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(am__DEPENDENCIES_4) \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(am__DEPENDENCIES_1)
erc32_sis_SOURCES = erc32/sis.c
erc32_sis_OBJECTS = erc32/sis.$(OBJEXT)
erc32_sis_LDADD = $(LDADD)
am_example_synacor_run_OBJECTS =
example_synacor_run_OBJECTS = $(am_example_synacor_run_OBJECTS)
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/nrun.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/libsim.a \
@SIM_ENABLE_ARCH_examples_TRUE@	$(am__DEPENDENCIES_4)
am_frv_run_OBJECTS =
frv_run_OBJECTS = $(am_frv_run_OBJECTS)
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_DEPENDENCIES = frv/nrun.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/libsim.a $(am__DEPENDENCIES_4)
am_ft32_run_OBJECTS =
ft32_run_OBJECTS = $(am_ft32_run_OBJECTS)
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_DEPENDENCIES = ft32/nrun.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/libsim.a $(am__DEPENDENCIES_4)
am_h8300_run_OBJECTS =
h8300_run_OBJECTS = $(am_h8300_run_OBJECTS)
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_DEPENDENCIES = h8300/nrun.o \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/libsim.a \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(am__DEPENDENCIES_4)
am_igen_filter_OBJECTS =
igen_filter_OBJECTS = $(am_igen_filter_OBJECTS)
igen_filter_DEPENDENCIES = igen/filter-main.o igen/libigen.a
am_igen_gen_OBJECTS =
igen_gen_OBJECTS = $(am_igen_gen_OBJECTS)
igen_gen_DEPENDENCIES = igen/gen-main.o igen/libigen.a
am_igen_igen_OBJECTS = igen/igen.$(OBJEXT)
igen_igen_OBJECTS = $(am_igen_igen_OBJECTS)
igen_igen_DEPENDENCIES = igen/libigen.a
am_igen_ld_cache_OBJECTS =
igen_ld_cache_OBJECTS = $(am_igen_ld_cache_OBJECTS)
igen_ld_cache_DEPENDENCIES = igen/ld-cache-main.o igen/libigen.a
am_igen_ld_decode_OBJECTS =
igen_ld_decode_OBJECTS = $(am_igen_ld_decode_OBJECTS)
igen_ld_decode_DEPENDENCIES = igen/ld-decode-main.o igen/libigen.a
am_igen_ld_insn_OBJECTS =
igen_ld_insn_OBJECTS = $(am_igen_ld_insn_OBJECTS)
igen_ld_insn_DEPENDENCIES = igen/ld-insn-main.o igen/libigen.a
am_igen_table_OBJECTS =
igen_table_OBJECTS = $(am_igen_table_OBJECTS)
igen_table_DEPENDENCIES = igen/table-main.o igen/libigen.a
am_iq2000_run_OBJECTS =
iq2000_run_OBJECTS = $(am_iq2000_run_OBJECTS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_DEPENDENCIES = iq2000/nrun.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/libsim.a \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(am__DEPENDENCIES_4)
am_lm32_run_OBJECTS =
lm32_run_OBJECTS = $(am_lm32_run_OBJECTS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_DEPENDENCIES = lm32/nrun.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_m32c_TRUE@am_m32c_opc2c_OBJECTS =  \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/opc2c.$(OBJEXT)
m32c_opc2c_OBJECTS = $(am_m32c_opc2c_OBJECTS)
m32c_opc2c_LDADD = $(LDADD)
am_m32c_run_OBJECTS =
m32c_run_OBJECTS = $(am_m32c_run_OBJECTS)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_DEPENDENCIES = m32c/main.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/libsim.a $(am__DEPENDENCIES_4)
am_m32r_run_OBJECTS =
m32r_run_OBJECTS = $(am_m32r_run_OBJECTS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_DEPENDENCIES = m32r/nrun.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am_m68hc11_gencode_OBJECTS =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/gencode.$(OBJEXT)
m68hc11_gencode_OBJECTS = $(am_m68hc11_gencode_OBJECTS)
m68hc11_gencode_LDADD = $(LDADD)
am_m68hc11_run_OBJECTS =
m68hc11_run_OBJECTS = $(am_m68hc11_run_OBJECTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/nrun.o m68hc11/libsim.a \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(am__DEPENDENCIES_4)
am_mcore_run_OBJECTS =
mcore_run_OBJECTS = $(am_mcore_run_OBJECTS)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_DEPENDENCIES = mcore/nrun.o \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/libsim.a \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(am__DEPENDENCIES_4)
am_microblaze_run_OBJECTS =
microblaze_run_OBJECTS = $(am_microblaze_run_OBJECTS)
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/nrun.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/libsim.a \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(am__DEPENDENCIES_4)
am_mips_run_OBJECTS =
mips_run_OBJECTS = $(am_mips_run_OBJECTS)
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_DEPENDENCIES = mips/nrun.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/libsim.a $(am__DEPENDENCIES_4)
am_mn10300_run_OBJECTS =
mn10300_run_OBJECTS = $(am_mn10300_run_OBJECTS)
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/nrun.o mn10300/libsim.a \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(am__DEPENDENCIES_4)
am_moxie_run_OBJECTS =
moxie_run_OBJECTS = $(am_moxie_run_OBJECTS)
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_DEPENDENCIES = moxie/nrun.o \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/libsim.a \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(am__DEPENDENCIES_4)
am_msp430_run_OBJECTS =
msp430_run_OBJECTS = $(am_msp430_run_OBJECTS)
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_DEPENDENCIES = msp430/nrun.o \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/libsim.a \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(am__DEPENDENCIES_4)
am_or1k_run_OBJECTS =
or1k_run_OBJECTS = $(am_or1k_run_OBJECTS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_DEPENDENCIES = or1k/nrun.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_igen_OBJECTS = ppc/igen.$(OBJEXT)
ppc_igen_OBJECTS = $(am_ppc_igen_OBJECTS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_DEPENDENCIES = ppc/libigen.a
am_ppc_ld_cache_OBJECTS =
ppc_ld_cache_OBJECTS = $(am_ppc_ld_cache_OBJECTS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-cache-main.o ppc/libigen.a
am_ppc_ld_decode_OBJECTS =
ppc_ld_decode_OBJECTS = $(am_ppc_ld_decode_OBJECTS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-decode-main.o ppc/libigen.a
am_ppc_ld_insn_OBJECTS =
ppc_ld_insn_OBJECTS = $(am_ppc_ld_insn_OBJECTS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-insn-main.o ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_run_OBJECTS = ppc/main.$(OBJEXT)
ppc_run_OBJECTS = $(am_ppc_run_OBJECTS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_DEPENDENCIES = ppc/libsim.a \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(am__DEPENDENCIES_4)
am_pru_run_OBJECTS =
pru_run_OBJECTS = $(am_pru_run_OBJECTS)
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_DEPENDENCIES = pru/nrun.o \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/libsim.a $(am__DEPENDENCIES_4)
am_riscv_run_OBJECTS =
riscv_run_OBJECTS = $(am_riscv_run_OBJECTS)
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_DEPENDENCIES = riscv/nrun.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/libsim.a \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(am__DEPENDENCIES_4)
am_rl78_run_OBJECTS =
rl78_run_OBJECTS = $(am_rl78_run_OBJECTS)
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_DEPENDENCIES = rl78/main.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/libsim.a $(am__DEPENDENCIES_4)
am_rx_run_OBJECTS =
rx_run_OBJECTS = $(am_rx_run_OBJECTS)
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_DEPENDENCIES = rx/main.o rx/libsim.a \
@SIM_ENABLE_ARCH_rx_TRUE@	$(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_sh_TRUE@am_sh_gencode_OBJECTS = sh/gencode.$(OBJEXT)
sh_gencode_OBJECTS = $(am_sh_gencode_OBJECTS)
sh_gencode_LDADD = $(LDADD)
am_sh_run_OBJECTS =
sh_run_OBJECTS = $(am_sh_run_OBJECTS)
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_DEPENDENCIES = sh/nrun.o sh/libsim.a \
@SIM_ENABLE_ARCH_sh_TRUE@	$(am__DEPENDENCIES_4)
testsuite_common_alu_tst_SOURCES = testsuite/common/alu-tst.c
testsuite_common_alu_tst_OBJECTS = testsuite/common/alu-tst.$(OBJEXT)
testsuite_common_alu_tst_LDADD = $(LDADD)
testsuite_common_bits_gen_SOURCES = testsuite/common/bits-gen.c
testsuite_common_bits_gen_OBJECTS =  \
	testsuite/common/bits-gen.$(OBJEXT)
testsuite_common_bits_gen_LDADD = $(LDADD)
testsuite_common_bits32m0_SOURCES = testsuite/common/bits32m0.c
testsuite_common_bits32m0_OBJECTS =  \
	testsuite/common/bits32m0.$(OBJEXT)
testsuite_common_bits32m0_LDADD = $(LDADD)
testsuite_common_bits32m31_SOURCES = testsuite/common/bits32m31.c
testsuite_common_bits32m31_OBJECTS =  \
	testsuite/common/bits32m31.$(OBJEXT)
testsuite_common_bits32m31_LDADD = $(LDADD)
testsuite_common_bits64m0_SOURCES = testsuite/common/bits64m0.c
testsuite_common_bits64m0_OBJECTS =  \
	testsuite/common/bits64m0.$(OBJEXT)
testsuite_common_bits64m0_LDADD = $(LDADD)
testsuite_common_bits64m63_SOURCES = testsuite/common/bits64m63.c
testsuite_common_bits64m63_OBJECTS =  \
	testsuite/common/bits64m63.$(OBJEXT)
testsuite_common_bits64m63_LDADD = $(LDADD)
testsuite_common_fpu_tst_SOURCES = testsuite/common/fpu-tst.c
testsuite_common_fpu_tst_OBJECTS = testsuite/common/fpu-tst.$(OBJEXT)
testsuite_common_fpu_tst_LDADD = $(LDADD)
am_v850_run_OBJECTS =
v850_run_OBJECTS = $(am_v850_run_OBJECTS)
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_DEPENDENCIES = v850/nrun.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/libsim.a $(am__DEPENDENCIES_4)
AM_V_P = $(am__v_P_@AM_V@)
am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
am__v_P_0 = false
am__v_P_1 = :
AM_V_GEN = $(am__v_GEN_@AM_V@)
am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
am__v_GEN_0 = @echo "  GEN     " $@;
am__v_GEN_1 = 
AM_V_at = $(am__v_at_@AM_V@)
am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
am__v_at_0 = @
am__v_at_1 = 
DEFAULT_INCLUDES = -I.@am__isrc@
depcomp = $(SHELL) $(top_srcdir)/../depcomp
am__depfiles_maybe = depfiles
am__mv = mv -f
COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
	$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
LTCOMPILE = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \
	$(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) \
	$(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \
	$(AM_CFLAGS) $(CFLAGS)
AM_V_CC = $(am__v_CC_@AM_V@)
am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
am__v_CC_0 = @echo "  CC      " $@;
am__v_CC_1 = 
CCLD = $(CC)
LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \
	$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
	$(AM_LDFLAGS) $(LDFLAGS) -o $@
AM_V_CCLD = $(am__v_CCLD_@AM_V@)
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo "  CCLD    " $@;
am__v_CCLD_1 = 
SOURCES = $(aarch64_libsim_a_SOURCES) \
	$(nodist_aarch64_libsim_a_SOURCES) $(arm_libsim_a_SOURCES) \
	$(nodist_arm_libsim_a_SOURCES) $(avr_libsim_a_SOURCES) \
	$(nodist_avr_libsim_a_SOURCES) $(bfin_libsim_a_SOURCES) \
	$(nodist_bfin_libsim_a_SOURCES) $(bpf_libsim_a_SOURCES) \
	$(nodist_bpf_libsim_a_SOURCES) $(common_libcommon_a_SOURCES) \
	$(cr16_libsim_a_SOURCES) $(nodist_cr16_libsim_a_SOURCES) \
	$(cris_libsim_a_SOURCES) $(nodist_cris_libsim_a_SOURCES) \
	$(d10v_libsim_a_SOURCES) $(nodist_d10v_libsim_a_SOURCES) \
	$(erc32_libsim_a_SOURCES) $(nodist_erc32_libsim_a_SOURCES) \
	$(example_synacor_libsim_a_SOURCES) \
	$(nodist_example_synacor_libsim_a_SOURCES) \
	$(frv_libsim_a_SOURCES) $(nodist_frv_libsim_a_SOURCES) \
	$(ft32_libsim_a_SOURCES) $(nodist_ft32_libsim_a_SOURCES) \
	$(h8300_libsim_a_SOURCES) $(nodist_h8300_libsim_a_SOURCES) \
	$(igen_libigen_a_SOURCES) $(iq2000_libsim_a_SOURCES) \
	$(nodist_iq2000_libsim_a_SOURCES) $(lm32_libsim_a_SOURCES) \
	$(nodist_lm32_libsim_a_SOURCES) $(m32c_libsim_a_SOURCES) \
	$(nodist_m32c_libsim_a_SOURCES) $(m32r_libsim_a_SOURCES) \
	$(nodist_m32r_libsim_a_SOURCES) $(m68hc11_libsim_a_SOURCES) \
	$(nodist_m68hc11_libsim_a_SOURCES) $(mcore_libsim_a_SOURCES) \
	$(nodist_mcore_libsim_a_SOURCES) \
	$(microblaze_libsim_a_SOURCES) \
	$(nodist_microblaze_libsim_a_SOURCES) $(mips_libsim_a_SOURCES) \
	$(nodist_mips_libsim_a_SOURCES) $(mn10300_libsim_a_SOURCES) \
	$(nodist_mn10300_libsim_a_SOURCES) $(moxie_libsim_a_SOURCES) \
	$(nodist_moxie_libsim_a_SOURCES) $(msp430_libsim_a_SOURCES) \
	$(nodist_msp430_libsim_a_SOURCES) $(or1k_libsim_a_SOURCES) \
	$(nodist_or1k_libsim_a_SOURCES) $(ppc_libigen_a_SOURCES) \
	$(ppc_libsim_a_SOURCES) $(pru_libsim_a_SOURCES) \
	$(nodist_pru_libsim_a_SOURCES) $(riscv_libsim_a_SOURCES) \
	$(nodist_riscv_libsim_a_SOURCES) $(rl78_libsim_a_SOURCES) \
	$(nodist_rl78_libsim_a_SOURCES) $(rx_libsim_a_SOURCES) \
	$(nodist_rx_libsim_a_SOURCES) $(sh_libsim_a_SOURCES) \
	$(nodist_sh_libsim_a_SOURCES) $(v850_libsim_a_SOURCES) \
	$(nodist_v850_libsim_a_SOURCES) $(aarch64_run_SOURCES) \
	$(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \
	$(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
	$(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \
	$(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \
	$(erc32_run_SOURCES) erc32/sis.c \
	$(example_synacor_run_SOURCES) $(frv_run_SOURCES) \
	$(ft32_run_SOURCES) $(h8300_run_SOURCES) \
	$(igen_filter_SOURCES) $(igen_gen_SOURCES) \
	$(igen_igen_SOURCES) $(igen_ld_cache_SOURCES) \
	$(igen_ld_decode_SOURCES) $(igen_ld_insn_SOURCES) \
	$(igen_table_SOURCES) $(iq2000_run_SOURCES) \
	$(lm32_run_SOURCES) $(m32c_opc2c_SOURCES) $(m32c_run_SOURCES) \
	$(m32r_run_SOURCES) $(m68hc11_gencode_SOURCES) \
	$(m68hc11_run_SOURCES) $(mcore_run_SOURCES) \
	$(microblaze_run_SOURCES) $(mips_run_SOURCES) \
	$(mn10300_run_SOURCES) $(moxie_run_SOURCES) \
	$(msp430_run_SOURCES) $(or1k_run_SOURCES) $(ppc_igen_SOURCES) \
	$(ppc_ld_cache_SOURCES) $(ppc_ld_decode_SOURCES) \
	$(ppc_ld_insn_SOURCES) $(ppc_run_SOURCES) $(pru_run_SOURCES) \
	$(riscv_run_SOURCES) $(rl78_run_SOURCES) $(rx_run_SOURCES) \
	$(sh_gencode_SOURCES) $(sh_run_SOURCES) \
	testsuite/common/alu-tst.c testsuite/common/bits-gen.c \
	testsuite/common/bits32m0.c testsuite/common/bits32m31.c \
	testsuite/common/bits64m0.c testsuite/common/bits64m63.c \
	testsuite/common/fpu-tst.c $(v850_run_SOURCES)
am__can_run_installinfo = \
  case $$AM_UPDATE_INFO_DIR in \
    n|no|NO) false;; \
    *) (install-info --version) >/dev/null 2>&1;; \
  esac
am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
am__vpath_adj = case $$p in \
    $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
    *) f=$$p;; \
  esac;
am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
am__install_max = 40
am__nobase_strip_setup = \
  srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
am__nobase_strip = \
  for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
am__nobase_list = $(am__nobase_strip_setup); \
  for p in $$list; do echo "$$p $$p"; done | \
  sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
  $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
    if (++n[$$2] == $(am__install_max)) \
      { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
    END { for (dir in files) print dir, files[dir] }'
am__base_list = \
  sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
  sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
am__uninstall_files_from_dir = { \
  test -z "$$files" \
    || { test ! -d "$$dir" && test ! -f "$$dir" && test ! -r "$$dir"; } \
    || { echo " ( cd '$$dir' && rm -f" $$files ")"; \
         $(am__cd) "$$dir" && rm -f $$files; }; \
  }
am__installdirs = "$(DESTDIR)$(armdocdir)" "$(DESTDIR)$(dtbdir)" \
	"$(DESTDIR)$(erc32docdir)" "$(DESTDIR)$(frvdocdir)" \
	"$(DESTDIR)$(or1kdocdir)" "$(DESTDIR)$(ppcdocdir)" \
	"$(DESTDIR)$(rxdocdir)" "$(DESTDIR)$(pkgincludedir)"
DATA = $(armdoc_DATA) $(dtb_DATA) $(erc32doc_DATA) $(frvdoc_DATA) \
	$(or1kdoc_DATA) $(ppcdoc_DATA) $(rxdoc_DATA)
am__pkginclude_HEADERS_DIST = $(srcroot)/include/sim/callback.h \
	$(srcroot)/include/sim/sim.h
HEADERS = $(pkginclude_HEADERS)
am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) \
	$(LISP)config.h.in
# Read a list of newline-separated strings from the standard input,
# and print each of them once, without duplicates.  Input order is
# *not* preserved.
am__uniquify_input = $(AWK) '\
  BEGIN { nonempty = 0; } \
  { items[$$0] = 1; nonempty = 1; } \
  END { if (nonempty) { for (i in items) print i; }; } \
'
# Make sure the list of sources is unique.  This is necessary because,
# e.g., the same source file might be shared among _SOURCES variables
# for different programs/libraries.
am__define_uniq_tagged_files = \
  list='$(am__tagged_files)'; \
  unique=`for i in $$list; do \
    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
  done | $(am__uniquify_input)`
ETAGS = etags
CTAGS = ctags
CSCOPE = cscope
AM_RECURSIVE_TARGETS = cscope check recheck
DEJATOOL = $(PACKAGE)
RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir
EXPECT = expect
RUNTEST = runtest
am__tty_colors_dummy = \
  mgn= red= grn= lgn= blu= brg= std=; \
  am__color_tests=no
am__tty_colors = { \
  $(am__tty_colors_dummy); \
  if test "X$(AM_COLOR_TESTS)" = Xno; then \
    am__color_tests=no; \
  elif test "X$(AM_COLOR_TESTS)" = Xalways; then \
    am__color_tests=yes; \
  elif test "X$$TERM" != Xdumb && { test -t 1; } 2>/dev/null; then \
    am__color_tests=yes; \
  fi; \
  if test $$am__color_tests = yes; then \
    red=''; \
    grn=''; \
    lgn=''; \
    blu=''; \
    mgn=''; \
    brg=''; \
    std=''; \
  fi; \
}
am__recheck_rx = ^[ 	]*:recheck:[ 	]*
am__global_test_result_rx = ^[ 	]*:global-test-result:[ 	]*
am__copy_in_global_log_rx = ^[ 	]*:copy-in-global-log:[ 	]*
# A command that, given a newline-separated list of test names on the
# standard input, print the name of the tests that are to be re-run
# upon "make recheck".
am__list_recheck_tests = $(AWK) '{ \
  recheck = 1; \
  while ((rc = (getline line < ($$0 ".trs"))) != 0) \
    { \
      if (rc < 0) \
        { \
          if ((getline line2 < ($$0 ".log")) < 0) \
	    recheck = 0; \
          break; \
        } \
      else if (line ~ /$(am__recheck_rx)[nN][Oo]/) \
        { \
          recheck = 0; \
          break; \
        } \
      else if (line ~ /$(am__recheck_rx)[yY][eE][sS]/) \
        { \
          break; \
        } \
    }; \
  if (recheck) \
    print $$0; \
  close ($$0 ".trs"); \
  close ($$0 ".log"); \
}'
# A command that, given a newline-separated list of test names on the
# standard input, create the global log from their .trs and .log files.
am__create_global_log = $(AWK) ' \
function fatal(msg) \
{ \
  print "fatal: making $@: " msg | "cat >&2"; \
  exit 1; \
} \
function rst_section(header) \
{ \
  print header; \
  len = length(header); \
  for (i = 1; i <= len; i = i + 1) \
    printf "="; \
  printf "\n\n"; \
} \
{ \
  copy_in_global_log = 1; \
  global_test_result = "RUN"; \
  while ((rc = (getline line < ($$0 ".trs"))) != 0) \
    { \
      if (rc < 0) \
         fatal("failed to read from " $$0 ".trs"); \
      if (line ~ /$(am__global_test_result_rx)/) \
        { \
          sub("$(am__global_test_result_rx)", "", line); \
          sub("[ 	]*$$", "", line); \
          global_test_result = line; \
        } \
      else if (line ~ /$(am__copy_in_global_log_rx)[nN][oO]/) \
        copy_in_global_log = 0; \
    }; \
  if (copy_in_global_log) \
    { \
      rst_section(global_test_result ": " $$0); \
      while ((rc = (getline line < ($$0 ".log"))) != 0) \
      { \
        if (rc < 0) \
          fatal("failed to read from " $$0 ".log"); \
        print line; \
      }; \
      printf "\n"; \
    }; \
  close ($$0 ".trs"); \
  close ($$0 ".log"); \
}'
# Restructured Text title.
am__rst_title = { sed 's/.*/   &   /;h;s/./=/g;p;x;s/ *$$//;p;g' && echo; }
# Solaris 10 'make', and several other traditional 'make' implementations,
# pass "-e" to $(SHELL), and POSIX 2008 even requires this.  Work around it
# by disabling -e (using the XSI extension "set +e") if it's set.
am__sh_e_setup = case $$- in *e*) set +e;; esac
# Default flags passed to test drivers.
am__common_driver_flags = \
  --color-tests "$$am__color_tests" \
  --enable-hard-errors "$$am__enable_hard_errors" \
  --expect-failure "$$am__expect_failure"
# To be inserted before the command running the test.  Creates the
# directory for the log if needed.  Stores in $dir the directory
# containing $f, in $tst the test, in $log the log.  Executes the
# developer- defined test setup AM_TESTS_ENVIRONMENT (if any), and
# passes TESTS_ENVIRONMENT.  Set up options for the wrapper that
# will run the test scripts (or their associated LOG_COMPILER, if
# thy have one).
am__check_pre = \
$(am__sh_e_setup);					\
$(am__vpath_adj_setup) $(am__vpath_adj)			\
$(am__tty_colors);					\
srcdir=$(srcdir); export srcdir;			\
case "$@" in						\
  */*) am__odir=`echo "./$@" | sed 's|/[^/]*$$||'`;;	\
    *) am__odir=.;; 					\
esac;							\
test "x$$am__odir" = x"." || test -d "$$am__odir" 	\
  || $(MKDIR_P) "$$am__odir" || exit $$?;		\
if test -f "./$$f"; then dir=./;			\
elif test -f "$$f"; then dir=;				\
else dir="$(srcdir)/"; fi;				\
tst=$$dir$$f; log='$@'; 				\
if test -n '$(DISABLE_HARD_ERRORS)'; then		\
  am__enable_hard_errors=no; 				\
else							\
  am__enable_hard_errors=yes; 				\
fi; 							\
case " $(XFAIL_TESTS) " in				\
  *[\ \	]$$f[\ \	]* | *[\ \	]$$dir$$f[\ \	]*) \
    am__expect_failure=yes;;				\
  *)							\
    am__expect_failure=no;;				\
esac; 							\
$(AM_TESTS_ENVIRONMENT) $(TESTS_ENVIRONMENT)
# A shell command to get the names of the tests scripts with any registered
# extension removed (i.e., equivalently, the names of the test logs, with
# the '.log' extension removed).  The result is saved in the shell variable
# '$bases'.  This honors runtime overriding of TESTS and TEST_LOGS.  Sadly,
# we cannot use something simpler, involving e.g., "$(TEST_LOGS:.log=)",
# since that might cause problem with VPATH rewrites for suffix-less tests.
# See also 'test-harness-vpath-rewrite.sh' and 'test-trs-basic.sh'.
am__set_TESTS_bases = \
  bases='$(TEST_LOGS)'; \
  bases=`for i in $$bases; do echo $$i; done | sed 's/\.log$$//'`; \
  bases=`echo $$bases`
RECHECK_LOGS = $(TEST_LOGS)
TEST_SUITE_LOG = test-suite.log
TEST_EXTENSIONS = @EXEEXT@ .test
LOG_DRIVER = $(SHELL) $(top_srcdir)/../test-driver
LOG_COMPILE = $(LOG_COMPILER) $(AM_LOG_FLAGS) $(LOG_FLAGS)
am__set_b = \
  case '$@' in \
    */*) \
      case '$*' in \
        */*) b='$*';; \
          *) b=`echo '$@' | sed 's/\.log$$//'`; \
       esac;; \
    *) \
      b='$*';; \
  esac
am__test_logs1 = $(TESTS:=.log)
am__test_logs2 = $(am__test_logs1:@EXEEXT@.log=.log)
TEST_LOGS = $(am__test_logs2:.test.log=.log)
TEST_LOG_DRIVER = $(SHELL) $(top_srcdir)/../test-driver
TEST_LOG_COMPILE = $(TEST_LOG_COMPILER) $(AM_TEST_LOG_FLAGS) \
	$(TEST_LOG_FLAGS)
ACLOCAL = @ACLOCAL@
AMTAR = @AMTAR@
AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
AR = @AR@
AR_FOR_BUILD = @AR_FOR_BUILD@
AS_FOR_TARGET = @AS_FOR_TARGET@
AS_FOR_TARGET_AARCH64 = @AS_FOR_TARGET_AARCH64@
AS_FOR_TARGET_ARM = @AS_FOR_TARGET_ARM@
AS_FOR_TARGET_AVR = @AS_FOR_TARGET_AVR@
AS_FOR_TARGET_BFIN = @AS_FOR_TARGET_BFIN@
AS_FOR_TARGET_BPF = @AS_FOR_TARGET_BPF@
AS_FOR_TARGET_CR16 = @AS_FOR_TARGET_CR16@
AS_FOR_TARGET_CRIS = @AS_FOR_TARGET_CRIS@
AS_FOR_TARGET_D10V = @AS_FOR_TARGET_D10V@
AS_FOR_TARGET_ERC32 = @AS_FOR_TARGET_ERC32@
AS_FOR_TARGET_EXAMPLE_SYNACOR = @AS_FOR_TARGET_EXAMPLE_SYNACOR@
AS_FOR_TARGET_FRV = @AS_FOR_TARGET_FRV@
AS_FOR_TARGET_FT32 = @AS_FOR_TARGET_FT32@
AS_FOR_TARGET_H8300 = @AS_FOR_TARGET_H8300@
AS_FOR_TARGET_IQ2000 = @AS_FOR_TARGET_IQ2000@
AS_FOR_TARGET_LM32 = @AS_FOR_TARGET_LM32@
AS_FOR_TARGET_M32C = @AS_FOR_TARGET_M32C@
AS_FOR_TARGET_M32R = @AS_FOR_TARGET_M32R@
AS_FOR_TARGET_M68HC11 = @AS_FOR_TARGET_M68HC11@
AS_FOR_TARGET_MCORE = @AS_FOR_TARGET_MCORE@
AS_FOR_TARGET_MICROBLAZE = @AS_FOR_TARGET_MICROBLAZE@
AS_FOR_TARGET_MIPS = @AS_FOR_TARGET_MIPS@
AS_FOR_TARGET_MN10300 = @AS_FOR_TARGET_MN10300@
AS_FOR_TARGET_MOXIE = @AS_FOR_TARGET_MOXIE@
AS_FOR_TARGET_MSP430 = @AS_FOR_TARGET_MSP430@
AS_FOR_TARGET_OR1K = @AS_FOR_TARGET_OR1K@
AS_FOR_TARGET_PPC = @AS_FOR_TARGET_PPC@
AS_FOR_TARGET_PRU = @AS_FOR_TARGET_PRU@
AS_FOR_TARGET_RISCV = @AS_FOR_TARGET_RISCV@
AS_FOR_TARGET_RL78 = @AS_FOR_TARGET_RL78@
AS_FOR_TARGET_RX = @AS_FOR_TARGET_RX@
AS_FOR_TARGET_SH = @AS_FOR_TARGET_SH@
AS_FOR_TARGET_V850 = @AS_FOR_TARGET_V850@
AUTOCONF = @AUTOCONF@
AUTOHEADER = @AUTOHEADER@
AUTOMAKE = @AUTOMAKE@
AWK = @AWK@
BUILD_WARN_CFLAGS = @BUILD_WARN_CFLAGS@
BUILD_WERROR_CFLAGS = @BUILD_WERROR_CFLAGS@
CC = @CC@
CCDEPMODE = @CCDEPMODE@
CC_FOR_BUILD = @CC_FOR_BUILD@
CC_FOR_TARGET = @CC_FOR_TARGET@
CC_FOR_TARGET_AARCH64 = @CC_FOR_TARGET_AARCH64@
CC_FOR_TARGET_ARM = @CC_FOR_TARGET_ARM@
CC_FOR_TARGET_AVR = @CC_FOR_TARGET_AVR@
CC_FOR_TARGET_BFIN = @CC_FOR_TARGET_BFIN@
CC_FOR_TARGET_BPF = @CC_FOR_TARGET_BPF@
CC_FOR_TARGET_CR16 = @CC_FOR_TARGET_CR16@
CC_FOR_TARGET_CRIS = @CC_FOR_TARGET_CRIS@
CC_FOR_TARGET_D10V = @CC_FOR_TARGET_D10V@
CC_FOR_TARGET_ERC32 = @CC_FOR_TARGET_ERC32@
CC_FOR_TARGET_EXAMPLE_SYNACOR = @CC_FOR_TARGET_EXAMPLE_SYNACOR@
CC_FOR_TARGET_FRV = @CC_FOR_TARGET_FRV@
CC_FOR_TARGET_FT32 = @CC_FOR_TARGET_FT32@
CC_FOR_TARGET_H8300 = @CC_FOR_TARGET_H8300@
CC_FOR_TARGET_IQ2000 = @CC_FOR_TARGET_IQ2000@
CC_FOR_TARGET_LM32 = @CC_FOR_TARGET_LM32@
CC_FOR_TARGET_M32C = @CC_FOR_TARGET_M32C@
CC_FOR_TARGET_M32R = @CC_FOR_TARGET_M32R@
CC_FOR_TARGET_M68HC11 = @CC_FOR_TARGET_M68HC11@
CC_FOR_TARGET_MCORE = @CC_FOR_TARGET_MCORE@
CC_FOR_TARGET_MICROBLAZE = @CC_FOR_TARGET_MICROBLAZE@
CC_FOR_TARGET_MIPS = @CC_FOR_TARGET_MIPS@
CC_FOR_TARGET_MN10300 = @CC_FOR_TARGET_MN10300@
CC_FOR_TARGET_MOXIE = @CC_FOR_TARGET_MOXIE@
CC_FOR_TARGET_MSP430 = @CC_FOR_TARGET_MSP430@
CC_FOR_TARGET_OR1K = @CC_FOR_TARGET_OR1K@
CC_FOR_TARGET_PPC = @CC_FOR_TARGET_PPC@
CC_FOR_TARGET_PRU = @CC_FOR_TARGET_PRU@
CC_FOR_TARGET_RISCV = @CC_FOR_TARGET_RISCV@
CC_FOR_TARGET_RL78 = @CC_FOR_TARGET_RL78@
CC_FOR_TARGET_RX = @CC_FOR_TARGET_RX@
CC_FOR_TARGET_SH = @CC_FOR_TARGET_SH@
CC_FOR_TARGET_V850 = @CC_FOR_TARGET_V850@
CFLAGS = @CFLAGS@
CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
CGEN_MAINT = @CGEN_MAINT@
CPP = @CPP@
CPPFLAGS = @CPPFLAGS@
CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
CYGPATH_W = @CYGPATH_W@
C_DIALECT = @C_DIALECT@
DEFS = @DEFS@
DEPDIR = @DEPDIR@
DSYMUTIL = @DSYMUTIL@
DTC = @DTC@
DUMPBIN = @DUMPBIN@
ECHO_C = @ECHO_C@
ECHO_N = @ECHO_N@
ECHO_T = @ECHO_T@
EGREP = @EGREP@
EXEEXT = @EXEEXT@
FGREP = @FGREP@
GREP = @GREP@
IGEN_FLAGS_SMP = @IGEN_FLAGS_SMP@
INSTALL = @INSTALL@
INSTALL_DATA = @INSTALL_DATA@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_SCRIPT = @INSTALL_SCRIPT@
INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
LD = @LD@
LDFLAGS = @LDFLAGS@
LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
LD_FOR_TARGET = @LD_FOR_TARGET@
LD_FOR_TARGET_AARCH64 = @LD_FOR_TARGET_AARCH64@
LD_FOR_TARGET_ARM = @LD_FOR_TARGET_ARM@
LD_FOR_TARGET_AVR = @LD_FOR_TARGET_AVR@
LD_FOR_TARGET_BFIN = @LD_FOR_TARGET_BFIN@
LD_FOR_TARGET_BPF = @LD_FOR_TARGET_BPF@
LD_FOR_TARGET_CR16 = @LD_FOR_TARGET_CR16@
LD_FOR_TARGET_CRIS = @LD_FOR_TARGET_CRIS@
LD_FOR_TARGET_D10V = @LD_FOR_TARGET_D10V@
LD_FOR_TARGET_ERC32 = @LD_FOR_TARGET_ERC32@
LD_FOR_TARGET_EXAMPLE_SYNACOR = @LD_FOR_TARGET_EXAMPLE_SYNACOR@
LD_FOR_TARGET_FRV = @LD_FOR_TARGET_FRV@
LD_FOR_TARGET_FT32 = @LD_FOR_TARGET_FT32@
LD_FOR_TARGET_H8300 = @LD_FOR_TARGET_H8300@
LD_FOR_TARGET_IQ2000 = @LD_FOR_TARGET_IQ2000@
LD_FOR_TARGET_LM32 = @LD_FOR_TARGET_LM32@
LD_FOR_TARGET_M32C = @LD_FOR_TARGET_M32C@
LD_FOR_TARGET_M32R = @LD_FOR_TARGET_M32R@
LD_FOR_TARGET_M68HC11 = @LD_FOR_TARGET_M68HC11@
LD_FOR_TARGET_MCORE = @LD_FOR_TARGET_MCORE@
LD_FOR_TARGET_MICROBLAZE = @LD_FOR_TARGET_MICROBLAZE@
LD_FOR_TARGET_MIPS = @LD_FOR_TARGET_MIPS@
LD_FOR_TARGET_MN10300 = @LD_FOR_TARGET_MN10300@
LD_FOR_TARGET_MOXIE = @LD_FOR_TARGET_MOXIE@
LD_FOR_TARGET_MSP430 = @LD_FOR_TARGET_MSP430@
LD_FOR_TARGET_OR1K = @LD_FOR_TARGET_OR1K@
LD_FOR_TARGET_PPC = @LD_FOR_TARGET_PPC@
LD_FOR_TARGET_PRU = @LD_FOR_TARGET_PRU@
LD_FOR_TARGET_RISCV = @LD_FOR_TARGET_RISCV@
LD_FOR_TARGET_RL78 = @LD_FOR_TARGET_RL78@
LD_FOR_TARGET_RX = @LD_FOR_TARGET_RX@
LD_FOR_TARGET_SH = @LD_FOR_TARGET_SH@
LD_FOR_TARGET_V850 = @LD_FOR_TARGET_V850@
LIBOBJS = @LIBOBJS@
LIBS = @LIBS@
LIBTOOL = @LIBTOOL@
LIPO = @LIPO@
LN_S = @LN_S@
LTLIBOBJS = @LTLIBOBJS@
MAINT = @MAINT@
MAKEINFO = @MAKEINFO@
MKDIR_P = @MKDIR_P@
NM = @NM@
NMEDIT = @NMEDIT@
OBJDUMP = @OBJDUMP@
OBJEXT = @OBJEXT@
OTOOL = @OTOOL@
OTOOL64 = @OTOOL64@
PACKAGE = @PACKAGE@
PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
PACKAGE_NAME = @PACKAGE_NAME@
PACKAGE_STRING = @PACKAGE_STRING@
PACKAGE_TARNAME = @PACKAGE_TARNAME@
PACKAGE_URL = @PACKAGE_URL@
PACKAGE_VERSION = @PACKAGE_VERSION@
PATH_SEPARATOR = @PATH_SEPARATOR@
PKGVERSION = @PKGVERSION@
PKG_CONFIG = @PKG_CONFIG@
PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
PKG_CONFIG_PATH = @PKG_CONFIG_PATH@
RANLIB = @RANLIB@
RANLIB_FOR_BUILD = @RANLIB_FOR_BUILD@
READLINE_CFLAGS = @READLINE_CFLAGS@
READLINE_LIB = @READLINE_LIB@
REPORT_BUGS_TEXI = @REPORT_BUGS_TEXI@
REPORT_BUGS_TO = @REPORT_BUGS_TO@
SDL_CFLAGS = @SDL_CFLAGS@
SDL_LIBS = @SDL_LIBS@
SED = @SED@
SET_MAKE = @SET_MAKE@
SHELL = @SHELL@
SIM_CFLAG_WNO_SHADOW_LOCAL = @SIM_CFLAG_WNO_SHADOW_LOCAL@
SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE = @SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE@
SIM_ENABLED_ARCHES = @SIM_ENABLED_ARCHES@
SIM_FRV_TRAPDUMP_FLAGS = @SIM_FRV_TRAPDUMP_FLAGS@
SIM_HW_CFLAGS = @SIM_HW_CFLAGS@
SIM_HW_SOCKSER = @SIM_HW_SOCKSER@
SIM_INLINE = @SIM_INLINE@
SIM_MIPS_BITSIZE = @SIM_MIPS_BITSIZE@
SIM_MIPS_FPU_BITSIZE = @SIM_MIPS_FPU_BITSIZE@
SIM_MIPS_GEN = @SIM_MIPS_GEN@
SIM_MIPS_IGEN_ITABLE_FLAGS = @SIM_MIPS_IGEN_ITABLE_FLAGS@
SIM_MIPS_M16_FLAGS = @SIM_MIPS_M16_FLAGS@
SIM_MIPS_MULTI_IGEN_CONFIGS = @SIM_MIPS_MULTI_IGEN_CONFIGS@
SIM_MIPS_MULTI_OBJ = @SIM_MIPS_MULTI_OBJ@
SIM_MIPS_MULTI_SRC = @SIM_MIPS_MULTI_SRC@
SIM_MIPS_SINGLE_FLAGS = @SIM_MIPS_SINGLE_FLAGS@
SIM_MIPS_SUBTARGET = @SIM_MIPS_SUBTARGET@
SIM_PRIMARY_TARGET = @SIM_PRIMARY_TARGET@
SIM_RISCV_BITSIZE = @SIM_RISCV_BITSIZE@
SIM_RX_CYCLE_ACCURATE_FLAGS = @SIM_RX_CYCLE_ACCURATE_FLAGS@
SIM_TOOLCHAIN_VARS = @SIM_TOOLCHAIN_VARS@
STRIP = @STRIP@
TERMCAP_LIB = @TERMCAP_LIB@
VERSION = @VERSION@
WARN_CFLAGS = @WARN_CFLAGS@
WERROR_CFLAGS = @WERROR_CFLAGS@
abs_builddir = @abs_builddir@
abs_srcdir = @abs_srcdir@
abs_top_builddir = @abs_top_builddir@
abs_top_srcdir = @abs_top_srcdir@
ac_ct_CC = @ac_ct_CC@
ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
am__include = @am__include@
am__leading_dot = @am__leading_dot@
am__quote = @am__quote@
am__tar = @am__tar@
am__untar = @am__untar@
bindir = @bindir@
build = @build@
build_alias = @build_alias@
build_cpu = @build_cpu@
build_os = @build_os@
build_vendor = @build_vendor@
builddir = @builddir@
cgen = @cgen@
cgendir = @cgendir@
datadir = @datadir@
datarootdir = @datarootdir@
docdir = @docdir@
dvidir = @dvidir@
exec_prefix = @exec_prefix@
host = @host@
host_alias = @host_alias@
host_cpu = @host_cpu@
host_os = @host_os@
host_vendor = @host_vendor@
htmldir = @htmldir@
includedir = @includedir@
infodir = @infodir@
install_sh = @install_sh@
libdir = @libdir@
libexecdir = @libexecdir@
localedir = @localedir@
localstatedir = @localstatedir@
mandir = @mandir@
mkdir_p = @mkdir_p@
oldincludedir = @oldincludedir@
pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
sim_ppc_bitsize = @sim_ppc_bitsize@
sim_ppc_decode_mechanism = @sim_ppc_decode_mechanism@
sim_ppc_default_model = @sim_ppc_default_model@
sim_ppc_dup = @sim_ppc_dup@
sim_ppc_filter = @sim_ppc_filter@
sim_ppc_float = @sim_ppc_float@
sim_ppc_hw_obj = @sim_ppc_hw_obj@
sim_ppc_hw_src = @sim_ppc_hw_src@
sim_ppc_icache = @sim_ppc_icache@
sim_ppc_igen_smp = @sim_ppc_igen_smp@
sim_ppc_jump = @sim_ppc_jump@
sim_ppc_line_nr = @sim_ppc_line_nr@
sim_ppc_model = @sim_ppc_model@
sim_ppc_model_issue = @sim_ppc_model_issue@
sim_ppc_monitor = @sim_ppc_monitor@
sim_ppc_opcode = @sim_ppc_opcode@
sim_ppc_smp = @sim_ppc_smp@
sim_ppc_switch = @sim_ppc_switch@
sim_ppc_timebase = @sim_ppc_timebase@
sim_ppc_xor_endian = @sim_ppc_xor_endian@
srcdir = @srcdir@
sysconfdir = @sysconfdir@
target = @target@
target_alias = @target_alias@
target_cpu = @target_cpu@
target_os = @target_os@
target_vendor = @target_vendor@
top_build_prefix = @top_build_prefix@
top_builddir = @top_builddir@
top_srcdir = @top_srcdir@
AUTOMAKE_OPTIONS = dejagnu foreign no-dist subdir-objects
ACLOCAL_AMFLAGS = -Im4 -I.. -I../config
GNULIB_PARENT_DIR = ..
srccom = $(srcdir)/common
srcroot = $(srcdir)/..
pkginclude_HEADERS = $(am__append_1)
EXTRA_LIBRARIES = igen/libigen.a $(am__append_101)
noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \
	$(am__append_7) $(am__append_9) $(am__append_11) \
	$(am__append_13) $(am__append_19) $(am__append_25) \
	$(am__append_31) $(am__append_35) $(am__append_37) \
	$(am__append_42) $(am__append_44) $(am__append_46) \
	$(am__append_51) $(am__append_56) $(am__append_60) \
	$(am__append_65) $(am__append_69) $(am__append_71) \
	$(am__append_76) $(am__append_84) $(am__append_88) \
	$(am__append_90) $(am__append_92) $(am__append_97) \
	$(am__append_103) $(am__append_105) $(am__append_107) \
	$(am__append_109) $(am__append_111) $(am__append_116)
BUILT_SOURCES = $(am__append_15) $(am__append_22) $(am__append_27) \
	$(am__append_39) $(am__append_48) $(am__append_53) \
	$(am__append_62) $(am__append_78) $(am__append_86) \
	$(am__append_94) $(am__append_99) $(am__append_113) \
	$(am__append_118)
CLEANFILES = common/version.c common/version.c-stamp \
	testsuite/common/bits-gen testsuite/common/bits32m0.c \
	testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
	testsuite/common/bits64m63.c $(am__append_17) $(am__append_23) \
	$(am__append_29) $(am__append_40) $(am__append_49) \
	$(am__append_54) $(am__append_63) $(am__append_95)
DISTCLEANFILES = $(am__append_83)
MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \
	$(SIM_ENABLED_ARCHES:%=%/hw-config.h) \
	$(SIM_ENABLED_ARCHES:%=%/stamp-hw) \
	$(SIM_ENABLED_ARCHES:%=%/modules.c) \
	$(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \
	igen/libigen.a site-sim-config.exp testrun.log testrun.sum \
	$(am__append_18) $(am__append_24) $(am__append_30) \
	$(am__append_41) $(am__append_50) $(am__append_55) \
	$(am__append_59) $(am__append_64) $(am__append_68) \
	$(am__append_82) $(am__append_87) $(am__append_96) \
	$(am__append_100) $(am__append_115) $(am__append_119)
CONFIG_STATUS_DEPENDENCIES = $(srcroot)/bfd/development.sh
AM_CFLAGS = \
	$(WERROR_CFLAGS) \
	$(WARN_CFLAGS) \
	$(AM_CFLAGS_$(subst -,_,$(@D))) \
	$(AM_CFLAGS_$(subst -,_,$(@D)_$(@F)))

AM_CPPFLAGS = $(INCGNU) -I$(srcroot) -I$(srcroot)/include -I../bfd \
	-I.. -I$(@D) -I$(srcdir)/$(@D) $(SIM_HW_CFLAGS) $(SIM_INLINE) \
	$(AM_CPPFLAGS_$(subst -,_,$(@D))) $(AM_CPPFLAGS_$(subst \
	-,_,$(@D)_$(@F))) -I$(srcdir)/common -DSIM_TOPDIR_BUILD
AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \
	$(SIM_INLINE) -I$(srcdir)/common
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(BUILD_WERROR_CFLAGS) $(BUILD_WARN_CFLAGS)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_INSTALL_DATA_LOCAL_DEPS = 
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_33)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_34)
SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
SIM_COMPILE = \
	$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \
	$(am__mv) $(SIM_DEPBASE).Tpo $(SIM_DEPBASE).Po

AM_CPPFLAGS_common = -DSIM_COMMON_BUILD
common_libcommon_a_SOURCES = \
	common/callback.c \
	common/portability.c \
	common/sim-load.c \
	common/sim-signal.c \
	common/syscall.c \
	common/target-newlib-errno.c \
	common/target-newlib-open.c \
	common/target-newlib-signal.c \
	common/target-newlib-syscall.c \
	common/version.c

SIM_COMMON_HW_OBJS = \
	hw-alloc.o \
	hw-base.o \
	hw-device.o \
	hw-events.o \
	hw-handles.o \
	hw-instances.o \
	hw-ports.o \
	hw-properties.o \
	hw-tree.o \
	sim-hw.o

SIM_NEW_COMMON_OBJS = sim-arange.o sim-bits.o sim-close.o \
	sim-command.o sim-config.o sim-core.o sim-cpu.o sim-endian.o \
	sim-engine.o sim-events.o sim-fpu.o sim-hload.o sim-hrw.o \
	sim-io.o sim-info.o sim-memopt.o sim-model.o sim-module.o \
	sim-options.o sim-profile.o sim-reason.o sim-reg.o sim-stop.o \
	sim-syscall.o sim-trace.o sim-utils.o sim-watch.o \
	$(am__append_2)
SIM_HW_DEVICES = cfi core pal glue
am_arch_d = $(subst -,_,$(@D))
GEN_MODULES_C_SRCS = \
	$(wildcard \
		$(patsubst %,$(srcdir)/%,$($(am_arch_d)_libsim_a_SOURCES)) \
		$(patsubst %.o,$(srcdir)/%.c,$($(am_arch_d)_libsim_a_OBJECTS) $($(am_arch_d)_libsim_a_LIBADD)) \
		$(filter-out %.o,$(patsubst $(@D)/%.o,$(srcdir)/common/%.c,$($(am_arch_d)_libsim_a_LIBADD))))

LIBIBERTY_LIB = ../libiberty/libiberty.a
BFD_LIB = ../bfd/libbfd.la
OPCODES_LIB = ../opcodes/libopcodes.la
SIM_COMMON_LIBS = \
	$(BFD_LIB) \
	$(OPCODES_LIB) \
	$(LIBIBERTY_LIB) \
	$(LIBGNU) \
	$(LIBGNU_EXTRA_LIBS)

GUILE = guile
CGEN = "$(GUILE) -l $(cgendir)/guile.scm -s"
CGENFLAGS = -v
CGEN_CPU_DIR = $(cgendir)/cpu
CPU_DIR = $(srcroot)/cpu
CGEN_ARCHFILE = $(CPU_DIR)/$(@D).cpu
CGEN_READ_SCM = $(cgendir)/sim.scm
CGEN_ARCH_SCM = $(cgendir)/sim-arch.scm
CGEN_CPU_SCM = $(cgendir)/sim-cpu.scm $(cgendir)/sim-model.scm
CGEN_DECODE_SCM = $(cgendir)/sim-decode.scm
CGEN_DESC_SCM = $(cgendir)/desc.scm $(cgendir)/desc-cpu.scm
CGEN_CPU_EXTR = /extr/
CGEN_CPU_READ = /read/
CGEN_CPU_WRITE = /write/
CGEN_CPU_SEM = /sem/
CGEN_CPU_SEMSW = /semsw/
CGEN_WRAPPER = $(srccom)/cgen.sh
CGEN_GEN_ARCH = \
	$(SHELL) $(CGEN_WRAPPER) arch $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" ignored "$$isa" $$mach ignored \
		$(CGEN_ARCHFILE) ignored

CGEN_GEN_CPU = \
	$(SHELL) $(CGEN_WRAPPER) cpu $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) "$$EXTRAFILES"

CGEN_GEN_DEFS = \
	$(SHELL) $(CGEN_WRAPPER) defs $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) ignored

CGEN_GEN_DECODE = \
	$(SHELL) $(CGEN_WRAPPER) decode $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) "$$EXTRAFILES"

CGEN_GEN_CPU_DECODE = \
	$(SHELL) $(CGEN_WRAPPER) cpu-decode $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) "$$EXTRAFILES"

CGEN_GEN_CPU_DESC = \
	$(SHELL) $(CGEN_WRAPPER) desc $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) ignored $$opcfile

CGEN_GEN_MLOOP = \
	$(SHELL) $(srccom)/lineno.sh \
		$(srccom)/genmloop.sh \
		$@.lineno.sh \
		-shell $(SHELL) -awk $(AWK) -lineno $(srccom)/lineno.sh \
		-infile $< -outfile-prefix $(@D)/


# igen leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
# leak detection while running it.
IGEN = igen/igen$(EXEEXT)
IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP)
igen_libigen_a_SOURCES = \
	igen/table.c \
	igen/lf.c \
	igen/misc.c \
	igen/filter_host.c \
	igen/ld-decode.c \
	igen/ld-cache.c \
	igen/filter.c \
	igen/ld-insn.c \
	igen/gen-model.c \
	igen/gen-itable.c \
	igen/gen-icache.c \
	igen/gen-semantics.c \
	igen/gen-idecode.c \
	igen/gen-support.c \
	igen/gen-engine.c \
	igen/gen.c

igen_igen_SOURCES = igen/igen.c
igen_igen_LDADD = igen/libigen.a
igen_filter_SOURCES = 
igen_filter_LDADD = igen/filter-main.o igen/libigen.a
igen_gen_SOURCES = 
igen_gen_LDADD = igen/gen-main.o igen/libigen.a
igen_ld_cache_SOURCES = 
igen_ld_cache_LDADD = igen/ld-cache-main.o igen/libigen.a
igen_ld_decode_SOURCES = 
igen_ld_decode_LDADD = igen/ld-decode-main.o igen/libigen.a
igen_ld_insn_SOURCES = 
igen_ld_insn_LDADD = igen/ld-insn-main.o igen/libigen.a
igen_table_SOURCES = 
igen_table_LDADD = igen/table-main.o igen/libigen.a
igen_IGEN_TOOLS = \
	$(IGEN) \
	igen/filter \
	igen/gen \
	igen/ld-cache \
	igen/ld-decode \
	igen/ld-insn \
	igen/table

EXTRA_DEJAGNU_SITE_CONFIG = site-sim-config.exp

# Custom verbose test variables that automake doesn't provide (yet?).
AM_V_RUNTEST = $(AM_V_RUNTEST_@AM_V@)
AM_V_RUNTEST_ = $(AM_V_RUNTEST_@AM_DEFAULT_V@)
AM_V_RUNTEST_0 = @echo "  RUNTEST  $(RUNTESTFLAGS) $*";
AM_V_RUNTEST_1 = 
DO_RUNTEST = \
	LC_ALL=C; export LC_ALL; \
	EXPECT=${EXPECT} ; export EXPECT ; \
	runtest=$(RUNTEST); \
	$$runtest $(RUNTESTFLAGS)

testsuite_common_CPPFLAGS = \
	-I$(srcdir)/common \
	-I$(srcroot)/include \
	-I../bfd

@SIM_ENABLE_ARCH_aarch64_TRUE@nodist_aarch64_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/modules.c

@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst %,aarch64/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst %,aarch64/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/cpustate.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/interp.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/memory.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/sim-resume.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/simulator.o

@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_SOURCES = 
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_LDADD = \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/nrun.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_arm_TRUE@AM_CPPFLAGS_arm = -DMODET
@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/modules.c

@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_arm_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/wrapper.o \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armvirt.o arm/thumbemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armcopro.o arm/maverick.o arm/iwmmxt.o

@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES = 
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/libsim.a \
@SIM_ENABLE_ARCH_arm_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm
@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README
@SIM_ENABLE_ARCH_avr_TRUE@nodist_avr_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/modules.c

@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_avr_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/interp.o \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst %,avr/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst %,avr/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/sim-resume.o

@SIM_ENABLE_ARCH_avr_TRUE@avr_run_SOURCES = 
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_LDADD = \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/nrun.o \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/libsim.a \
@SIM_ENABLE_ARCH_avr_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_bfin_TRUE@AM_CPPFLAGS_bfin = $(SDL_CFLAGS)
@SIM_ENABLE_ARCH_bfin_TRUE@nodist_bfin_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/modules.c

@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst %,bfin/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst %,bfin/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst %,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/bfin-sim.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/devices.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/gui.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/interp.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/machs.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/sim-resume.o

@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_SOURCES = 
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_LDADD = \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/nrun.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/libsim.a \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_bfin_TRUE@bfin_SIM_EXTRA_HW_DEVICES = \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_cec \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ctimer \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_dma \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_dmac \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ebiu_amc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ebiu_ddrc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ebiu_sdc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_emac \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_eppi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_evt \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_gpio \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_gpio2 \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_gptimer \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_jtag \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_mmu \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_nfc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_otp \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_pfmon \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_pint \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_pll \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ppi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_rtc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_sic \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_spi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_trace \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_twi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_uart \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_uart2 \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_wdog \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_wp \
@SIM_ENABLE_ARCH_bfin_TRUE@	eth_phy

@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/modules.c

@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/bpf-sim.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/sim-resume.o

@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES = 
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/nrun.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/libsim.a \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/modules.c

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(patsubst %,cr16/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(patsubst %,cr16/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/interp.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/sim-resume.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/simops.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/table.o

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_SOURCES = 
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_LDADD = \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/nrun.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/libsim.a \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/table.c

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(SIM_CFLAG_WNO_SHADOW_LOCAL)
@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv32f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE)
@SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modules.c

@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cris_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst %,cris/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst %,cris/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst %,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	\
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-run.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-scache.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-trace.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-utils.o \
@SIM_ENABLE_ARCH_cris_TRUE@	\
@SIM_ENABLE_ARCH_cris_TRUE@	cris/arch.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/crisv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cpuv10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/decodev10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modelv10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/crisv32f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cpuv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/decodev32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modelv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv32f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	\
@SIM_ENABLE_ARCH_cris_TRUE@	cris/sim-if.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/traps.o

@SIM_ENABLE_ARCH_cris_TRUE@cris_run_SOURCES = 
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_LDADD = \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/nrun.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/libsim.a \
@SIM_ENABLE_ARCH_cris_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_cris_TRUE@cris_SIM_EXTRA_HW_DEVICES = rv cris cris_900000xx
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_SOURCES = cris/rvdummy.c
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_LDADD = $(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_cris_TRUE@cris_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv10f.c \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/stamp-mloop-v10f \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv32f.c \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/stamp-mloop-v32f

@SIM_ENABLE_ARCH_d10v_TRUE@nodist_d10v_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/modules.c

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/interp.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(patsubst %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(patsubst %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/endian.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/sim-resume.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/simops.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/table.o

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES = 
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD = \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/nrun.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/libsim.a \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/table.c

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD = d10v/d10v-opc.o
@SIM_ENABLE_ARCH_erc32_TRUE@READLINE_SRC = $(srcroot)/readline/readline
@SIM_ENABLE_ARCH_erc32_TRUE@AM_CPPFLAGS_erc32 = $(READLINE_CFLAGS) \
@SIM_ENABLE_ARCH_erc32_TRUE@	-DFAST_UART
@SIM_ENABLE_ARCH_erc32_TRUE@nodist_erc32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/modules.c

@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/erc32.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/exec.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/float.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/func.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/help.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/interf.o

@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES = 
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD = \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/sis.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/libsim.a \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(SIM_COMMON_LIBS) $(READLINE_LIB) $(TERMCAP_LIB)

@SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32
@SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis
@SIM_ENABLE_ARCH_examples_TRUE@nodist_example_synacor_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/modules.c

@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_examples_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/interp.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-main.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-resume.o

@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES = 
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/nrun.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/libsim.a \
@SIM_ENABLE_ARCH_examples_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_frv_TRUE@AM_CPPFLAGS_frv = $(SIM_FRV_TRAPDUMP_FLAGS)
@SIM_ENABLE_ARCH_frv_TRUE@nodist_frv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/modules.c

@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_frv_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_frv_TRUE@	$(patsubst %,frv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_frv_TRUE@	$(patsubst %,frv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_frv_TRUE@	\
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-accfp.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-fpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-run.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-scache.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-trace.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-utils.o \
@SIM_ENABLE_ARCH_frv_TRUE@	\
@SIM_ENABLE_ARCH_frv_TRUE@	frv/arch.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-par.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/decode.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/frv.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/mloop.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/model.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/sem.o \
@SIM_ENABLE_ARCH_frv_TRUE@	\
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cache.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/interrupts.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/memory.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/options.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/pipeline.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr400.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr450.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr500.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr550.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/registers.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/reset.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/sim-if.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/traps.o

@SIM_ENABLE_ARCH_frv_TRUE@frv_run_SOURCES = 
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_LDADD = \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/nrun.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/libsim.a \
@SIM_ENABLE_ARCH_frv_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_frv_TRUE@frvdocdir = $(docdir)/frv
@SIM_ENABLE_ARCH_frv_TRUE@frvdoc_DATA = frv/README
@SIM_ENABLE_ARCH_frv_TRUE@frv_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/mloop.c \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/stamp-mloop

@SIM_ENABLE_ARCH_ft32_TRUE@nodist_ft32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/modules.c

@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/interp.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/sim-resume.o

@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES = 
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/nrun.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/libsim.a \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_h8300_TRUE@nodist_h8300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/modules.c

@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/compile.o \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(patsubst %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(patsubst %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/sim-resume.o

@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_SOURCES = 
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_LDADD = \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/nrun.o \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/libsim.a \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_iq2000_TRUE@nodist_iq2000_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/modules.c

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	\
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-run.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-scache.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-trace.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-utils.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	\
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/arch.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cpu.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/decode.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/iq2000.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/sem.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/mloop.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/model.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	\
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/sim-if.o

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES = 
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/nrun.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/libsim.a \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/mloop.c \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/stamp-mloop

@SIM_ENABLE_ARCH_lm32_TRUE@nodist_lm32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/modules.c

@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	\
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-run.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-scache.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-trace.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-utils.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	\
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/arch.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cpu.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/decode.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/sem.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/mloop.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/model.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	\
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/lm32.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/sim-if.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/traps.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/user.o

@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES = 
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/nrun.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/libsim.a \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_lm32_TRUE@lm32_SIM_EXTRA_HW_DEVICES = lm32cpu lm32timer lm32uart
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/mloop.c \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/stamp-mloop

@SIM_ENABLE_ARCH_m32c_TRUE@AM_CPPFLAGS_m32c = -DTIMER_A
@SIM_ENABLE_ARCH_m32c_TRUE@nodist_m32c_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/modules.c

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/gdb-if.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/int.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/load.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/mem.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/misc.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/reg.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/srcdest.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/syscalls.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/trace.o

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES = 
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/main.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/libsim.a \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/opc2c$(EXEEXT) \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.c \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.c

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_opc2c_SOURCES = m32c/opc2c.c

# opc2c leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/modules.c

@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-run.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-scache.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-trace.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-utils.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/arch.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32r.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpu.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decode.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/sem.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32rx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpux.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decodex.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/modelx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloopx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32r2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpu2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decode2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/sim-if.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/traps.o

@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES = 
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/nrun.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/libsim.a \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_m32r_TRUE@m32r_SIM_EXTRA_HW_DEVICES = m32r_cache m32r_uart
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop.c \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/stamp-mloop \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloopx.c \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/stamp-mloop-x \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop2.c \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/stamp-mloop-2

@SIM_ENABLE_ARCH_m68hc11_TRUE@AM_CPPFLAGS_m68hc11 = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	-DWITH_TARGET_WORD_BITSIZE=32 \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	-DWITH_TARGET_CELL_BITSIZE=32 \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	-DWITH_TARGET_ADDRESS_BITSIZE=32 \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	-DWITH_TARGET_WORD_MSB=31

@SIM_ENABLE_ARCH_m68hc11_TRUE@nodist_m68hc11_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/modules.c

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interp.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc12int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/emulos.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interrupts.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11_sim.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/sim-resume.o

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES = 
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/nrun.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/libsim.a \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_SIM_EXTRA_HW_DEVICES = m68hc11 m68hc11sio m68hc11eepr m68hc11tim m68hc11spi nvram
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11int.c \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc12int.c

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
@SIM_ENABLE_ARCH_mcore_TRUE@nodist_mcore_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/modules.c

@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/interp.o \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/sim-resume.o

@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES = 
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/nrun.o \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/libsim.a \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_microblaze_TRUE@nodist_microblaze_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/modules.c

@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/interp.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/sim-resume.o

@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES = 
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/nrun.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/libsim.a \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_mips_TRUE@AM_CPPFLAGS_mips = \
@SIM_ENABLE_ARCH_mips_TRUE@	@SIM_MIPS_SUBTARGET@ \
@SIM_ENABLE_ARCH_mips_TRUE@	-DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
@SIM_ENABLE_ARCH_mips_TRUE@	-DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@

@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_74) $(am__append_75)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/modules.c

@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@	$(mips_GEN_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst %,mips/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst %,mips/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/cp1.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/dsp.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mdmx.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sim-main.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sim-resume.o

@SIM_ENABLE_ARCH_mips_TRUE@EXTRA_mips_libsim_a_DEPENDENCIES = $(SIM_MIPS_MULTI_OBJ)
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES = 
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/nrun.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/libsim.a \
@SIM_ENABLE_ARCH_mips_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_mips_TRUE@mips_SIM_EXTRA_HW_DEVICES = tx3904cpu tx3904irc tx3904tmr tx3904sio
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_IGEN_ITABLE = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/itable.c

@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_SINGLE = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/model.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/model.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/support.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/support.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/engine.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/engine.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/irun.c

@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M16 = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_support.c \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M32 = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_support.c

@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =  \
@SIM_ENABLE_ARCH_mips_TRUE@	$(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/stamp-igen-itable \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_79) $(am__append_80) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_81)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/dsp.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/dsp2.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16e.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mdmx.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/micromipsdsp.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/micromips.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mips3264r2.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mips3264r6.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mips3d.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sb1.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/tx.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/vr.igen

@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_DC = $(srcdir)/mips/mips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS32_DC = $(srcdir)/mips/micromips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS16_DC = $(srcdir)/mips/micromips16.dc
@SIM_ENABLE_ARCH_mn10300_TRUE@AM_CPPFLAGS_mn10300 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	-DPOLL_QUIT_INTERVAL=0x20 \
@SIM_ENABLE_ARCH_mn10300_TRUE@	-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31

@SIM_ENABLE_ARCH_mn10300_TRUE@nodist_mn10300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/modules.c

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/irun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(patsubst %,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(patsubst %,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(patsubst %,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/interp.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/op_utils.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/sim-resume.o

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES = 
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/nrun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/libsim.a \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_SIM_EXTRA_HW_DEVICES = mn103cpu mn103int mn103tim mn103ser mn103iop
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/model.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/model.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/irun.c

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(mn10300_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/stamp-igen

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN = $(srcdir)/mn10300/mn10300.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN_INC = mn10300/am33.igen mn10300/am33-2.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_DC = $(srcdir)/mn10300/mn10300.dc
@SIM_ENABLE_ARCH_moxie_TRUE@AM_CPPFLAGS_moxie = -DDTB="\"$(dtbdir)/moxie-gdb.dtb\""
@SIM_ENABLE_ARCH_moxie_TRUE@nodist_moxie_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/modules.c

@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(patsubst %,moxie/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(patsubst %,moxie/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/interp.o \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/sim-resume.o

@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_SOURCES = 
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_LDADD = \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/nrun.o \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/libsim.a \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_moxie_TRUE@dtbdir = $(datadir)/gdb/dtb
@SIM_ENABLE_ARCH_moxie_TRUE@dtb_DATA = moxie/moxie-gdb.dtb
@SIM_ENABLE_ARCH_msp430_TRUE@nodist_msp430_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/modules.c

@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(patsubst %,msp430/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(patsubst %,msp430/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/msp430-sim.o \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/sim-resume.o

@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_SOURCES = 
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_LDADD = \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/nrun.o \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/libsim.a \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_or1k_TRUE@AM_CPPFLAGS_or1k = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31
@SIM_ENABLE_ARCH_or1k_TRUE@nodist_or1k_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/modules.c

@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_or1k_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_or1k_TRUE@	$(patsubst %,or1k/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_or1k_TRUE@	$(patsubst %,or1k/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_or1k_TRUE@	\
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-accfp.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-fpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-run.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-scache.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-trace.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cgen-utils.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	\
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/arch.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/cpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/decode.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/mloop.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/model.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/sem.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	\
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/or1k.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/sim-if.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/traps.o

@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_SOURCES = 
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_LDADD = \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/nrun.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/libsim.a \
@SIM_ENABLE_ARCH_or1k_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_or1k_TRUE@or1kdocdir = $(docdir)/or1k
@SIM_ENABLE_ARCH_or1k_TRUE@or1kdoc_DATA = or1k/README
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/mloop.c \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/stamp-mloop

@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc = \
@SIM_ENABLE_ARCH_ppc_TRUE@	-DHAVE_COMMON_FPU \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_smp) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_xor_endian) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_bitsize) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_timebase) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_float) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_monitor) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_model) $(sim_ppc_default_model) $(sim_ppc_model_issue) \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(sim_ppc_switch)

@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc_options.o = '-DOPCODE_RULES="$(IGEN_OPCODE_RULES)"' '-DIGEN_FLAGS="$(ppc_IGEN_FLAGS)"'
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/debug.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/bits.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/sim-endian.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/os_emul.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/emul_generic.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/emul_bugapi.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/emul_chirp.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/emul_netbsd.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/emul_unix.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/registers.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/vm.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/corefile.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/model.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/spreg.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/cpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/interrupts.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/events.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/cap.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/device.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/tree.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/device_table.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/itable.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/mon.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/icache.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/semantics.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/idecode.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/support.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/sim-fpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/psim.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/pk_disklabel.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(patsubst %,ppc/%,$(sim_ppc_hw_obj)) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/options.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gdb-sim.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/sim_calls.o

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES = \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/main.c

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_LDADD = \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/libsim.a \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_SOURCES = \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/table.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/lf-ppc.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/dumpf.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-decode.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-cache.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/filter-ppc.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-insn.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-model.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-itable.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-icache.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-semantics.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-idecode.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/gen-support.c

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_LIBADD = \
@SIM_ENABLE_ARCH_ppc_TRUE@	igen/filter.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	igen/filter_host.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	igen/lf.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	igen/misc.o

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_SOURCES = ppc/igen.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_LDADD = ppc/libigen.a

# igen leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN = ppc/igen$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(PPC_IGEN) $(ppc_IGEN_FLAGS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_FLAGS = \
@SIM_ENABLE_ARCH_ppc_TRUE@	@sim_ppc_decode_mechanism@ \
@SIM_ENABLE_ARCH_ppc_TRUE@	@sim_ppc_dup@ \
@SIM_ENABLE_ARCH_ppc_TRUE@	@sim_ppc_jump@ \
@SIM_ENABLE_ARCH_ppc_TRUE@	@sim_ppc_filter@ \
@SIM_ENABLE_ARCH_ppc_TRUE@	@sim_ppc_icache@ \
@SIM_ENABLE_ARCH_ppc_TRUE@	@sim_ppc_igen_smp@ \
@SIM_ENABLE_ARCH_ppc_TRUE@	@sim_ppc_line_nr@

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/icache.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/icache.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/idecode.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/idecode.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/semantics.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/semantics.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/model.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/model.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/support.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/support.c \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/itable.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/itable.c

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILD_OUTPUTS =  \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(ppc_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/stamp-igen ppc/hw.c ppc/hw.h \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/stamp-hw ppc/stamp-pk
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_OPCODE_RULES = ppc/@sim_ppc_opcode@
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_SOURCES = 
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_LDADD = ppc/ld-cache-main.o ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_SOURCES = 
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_LDADD = ppc/ld-decode-main.o ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_SOURCES = 
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_LDADD = ppc/ld-insn-main.o ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_TOOLS = \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(PPC_IGEN) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-cache \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-decode \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/ld-insn

@SIM_ENABLE_ARCH_ppc_TRUE@IGEN_OPCODE_RULES = @sim_ppc_opcode@
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_HW_SRC = $(sim_ppc_hw_src:%=ppc/%)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_PACKAGE_SRC = ppc/pk_disklabel.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir = $(docdir)/ppc
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA = ppc/BUGS ppc/INSTALL ppc/README ppc/RUN
@SIM_ENABLE_ARCH_pru_TRUE@nodist_pru_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/modules.c

@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_pru_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_pru_TRUE@	$(patsubst %,pru/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_pru_TRUE@	$(patsubst %,pru/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/interp.o \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/sim-resume.o

@SIM_ENABLE_ARCH_pru_TRUE@pru_run_SOURCES = 
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_LDADD = \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/nrun.o \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/libsim.a \
@SIM_ENABLE_ARCH_pru_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_riscv_TRUE@AM_CPPFLAGS_riscv = -DWITH_TARGET_WORD_BITSIZE=$(SIM_RISCV_BITSIZE)
@SIM_ENABLE_ARCH_riscv_TRUE@nodist_riscv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/modules.c

@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(patsubst %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(patsubst %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/interp.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/machs.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/sim-main.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/sim-resume.o

@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_SOURCES = 
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_LDADD = \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/nrun.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/libsim.a \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_rl78_TRUE@nodist_rl78_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/modules.c

@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rl78_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/load.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/mem.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/cpu.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/rl78.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/gdb-if.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/trace.o

@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_SOURCES = 
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_LDADD = \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/main.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/libsim.a \
@SIM_ENABLE_ARCH_rl78_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_rx_TRUE@AM_CPPFLAGS_rx = $(SIM_RX_CYCLE_ACCURATE_FLAGS)
@SIM_ENABLE_ARCH_rx_TRUE@nodist_rx_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/modules.c

@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rx_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/fpu.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/load.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/mem.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/misc.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/reg.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/rx.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/syscalls.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/trace.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/gdb-if.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/err.o

@SIM_ENABLE_ARCH_rx_TRUE@rx_run_SOURCES = 
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_LDADD = \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/main.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/libsim.a \
@SIM_ENABLE_ARCH_rx_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_rx_TRUE@rxdocdir = $(docdir)/rx
@SIM_ENABLE_ARCH_rx_TRUE@rxdoc_DATA = rx/README.txt
@SIM_ENABLE_ARCH_sh_TRUE@nodist_sh_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/modules.c

@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_sh_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/interp.o \
@SIM_ENABLE_ARCH_sh_TRUE@	$(patsubst %,sh/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_sh_TRUE@	$(patsubst %,sh/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/table.o

@SIM_ENABLE_ARCH_sh_TRUE@sh_run_SOURCES = 
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_LDADD = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/nrun.o \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/libsim.a \
@SIM_ENABLE_ARCH_sh_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_sh_TRUE@sh_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/ppi.c \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/table.c

@SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c
@SIM_ENABLE_ARCH_v850_TRUE@AM_CPPFLAGS_v850 = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31
@SIM_ENABLE_ARCH_v850_TRUE@nodist_v850_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/modules.c

@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_v850_TRUE@	$(common_libcommon_a_SOURCES)

@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_v850_TRUE@	$(patsubst %,v850/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_v850_TRUE@	$(patsubst %,v850/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/simops.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/interp.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/irun.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/sim-resume.o

@SIM_ENABLE_ARCH_v850_TRUE@v850_run_SOURCES = 
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_LDADD = \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/nrun.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/libsim.a \
@SIM_ENABLE_ARCH_v850_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/model.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/model.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/irun.c

@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_v850_TRUE@	$(v850_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/stamp-igen

@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_INSN = $(srcdir)/v850/v850.igen
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_DC = $(srcdir)/v850/v850.dc
all: $(BUILT_SOURCES) config.h
	$(MAKE) $(AM_MAKEFLAGS) all-am

.SUFFIXES:
.SUFFIXES: .c .lo .log .o .obj .test .test$(EXEEXT) .trs
am--refresh: Makefile
	@:
$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__configure_deps)
	@for dep in $?; do \
	  case '$(am__configure_deps)' in \
	    *$$dep*) \
	      echo ' cd $(srcdir) && $(AUTOMAKE) --foreign'; \
	      $(am__cd) $(srcdir) && $(AUTOMAKE) --foreign \
		&& exit 0; \
	      exit 1;; \
	  esac; \
	done; \
	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \
	$(am__cd) $(top_srcdir) && \
	  $(AUTOMAKE) --foreign Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
	@case '$?' in \
	  *config.status*) \
	    echo ' $(SHELL) ./config.status'; \
	    $(SHELL) ./config.status;; \
	  *) \
	    echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \
	    cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \
	esac;
$(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__empty):

$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
	$(SHELL) ./config.status --recheck

$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
	$(am__cd) $(srcdir) && $(AUTOCONF)
$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
	$(am__cd) $(srcdir) && $(ACLOCAL) $(ACLOCAL_AMFLAGS)
$(am__aclocal_m4_deps):

config.h: stamp-h1
	@test -f $@ || rm -f stamp-h1
	@test -f $@ || $(MAKE) $(AM_MAKEFLAGS) stamp-h1

stamp-h1: $(srcdir)/config.h.in $(top_builddir)/config.status
	@rm -f stamp-h1
	cd $(top_builddir) && $(SHELL) ./config.status config.h
$(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) 
	($(am__cd) $(top_srcdir) && $(AUTOHEADER))
	rm -f stamp-h1
	touch $@

distclean-hdr:
	-rm -f config.h stamp-h1
aarch64/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
arm/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
avr/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
bfin/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
bpf/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
cr16/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
cris/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
d10v/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
frv/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
ft32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
h8300/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
iq2000/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
lm32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
m32c/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
m32r/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
m68hc11/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
mcore/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
microblaze/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
mips/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
mn10300/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
moxie/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
msp430/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
or1k/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
ppc/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
pru/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
riscv/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
rl78/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
rx/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
sh/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
erc32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
v850/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
example-synacor/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@
.gdbinit: $(top_builddir)/config.status $(srcdir)/gdbinit.in
	cd $(top_builddir) && $(SHELL) ./config.status $@

clean-noinstLIBRARIES:
	-test -z "$(noinst_LIBRARIES)" || rm -f $(noinst_LIBRARIES)
common/$(am__dirstamp):
	@$(MKDIR_P) common
	@: > common/$(am__dirstamp)
common/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) common/$(DEPDIR)
	@: > common/$(DEPDIR)/$(am__dirstamp)
common/callback.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/portability.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/sim-load.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/sim-signal.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/syscall.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/target-newlib-errno.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/target-newlib-open.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/target-newlib-signal.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/target-newlib-syscall.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
common/version.$(OBJEXT): common/$(am__dirstamp) \
	common/$(DEPDIR)/$(am__dirstamp)
aarch64/$(am__dirstamp):
	@$(MKDIR_P) aarch64
	@: > aarch64/$(am__dirstamp)
aarch64/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) aarch64/$(DEPDIR)
	@: > aarch64/$(DEPDIR)/$(am__dirstamp)
aarch64/modules.$(OBJEXT): aarch64/$(am__dirstamp) \
	aarch64/$(DEPDIR)/$(am__dirstamp)

aarch64/libsim.a: $(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_DEPENDENCIES) $(EXTRA_aarch64_libsim_a_DEPENDENCIES) aarch64/$(am__dirstamp)
	$(AM_V_at)-rm -f aarch64/libsim.a
	$(AM_V_AR)$(aarch64_libsim_a_AR) aarch64/libsim.a $(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) aarch64/libsim.a
arm/$(am__dirstamp):
	@$(MKDIR_P) arm
	@: > arm/$(am__dirstamp)
arm/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) arm/$(DEPDIR)
	@: > arm/$(DEPDIR)/$(am__dirstamp)
arm/modules.$(OBJEXT): arm/$(am__dirstamp) \
	arm/$(DEPDIR)/$(am__dirstamp)

arm/libsim.a: $(arm_libsim_a_OBJECTS) $(arm_libsim_a_DEPENDENCIES) $(EXTRA_arm_libsim_a_DEPENDENCIES) arm/$(am__dirstamp)
	$(AM_V_at)-rm -f arm/libsim.a
	$(AM_V_AR)$(arm_libsim_a_AR) arm/libsim.a $(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) arm/libsim.a
avr/$(am__dirstamp):
	@$(MKDIR_P) avr
	@: > avr/$(am__dirstamp)
avr/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) avr/$(DEPDIR)
	@: > avr/$(DEPDIR)/$(am__dirstamp)
avr/modules.$(OBJEXT): avr/$(am__dirstamp) \
	avr/$(DEPDIR)/$(am__dirstamp)

avr/libsim.a: $(avr_libsim_a_OBJECTS) $(avr_libsim_a_DEPENDENCIES) $(EXTRA_avr_libsim_a_DEPENDENCIES) avr/$(am__dirstamp)
	$(AM_V_at)-rm -f avr/libsim.a
	$(AM_V_AR)$(avr_libsim_a_AR) avr/libsim.a $(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) avr/libsim.a
bfin/$(am__dirstamp):
	@$(MKDIR_P) bfin
	@: > bfin/$(am__dirstamp)
bfin/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) bfin/$(DEPDIR)
	@: > bfin/$(DEPDIR)/$(am__dirstamp)
bfin/modules.$(OBJEXT): bfin/$(am__dirstamp) \
	bfin/$(DEPDIR)/$(am__dirstamp)

bfin/libsim.a: $(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_DEPENDENCIES) $(EXTRA_bfin_libsim_a_DEPENDENCIES) bfin/$(am__dirstamp)
	$(AM_V_at)-rm -f bfin/libsim.a
	$(AM_V_AR)$(bfin_libsim_a_AR) bfin/libsim.a $(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) bfin/libsim.a
bpf/$(am__dirstamp):
	@$(MKDIR_P) bpf
	@: > bpf/$(am__dirstamp)
bpf/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) bpf/$(DEPDIR)
	@: > bpf/$(DEPDIR)/$(am__dirstamp)
bpf/modules.$(OBJEXT): bpf/$(am__dirstamp) \
	bpf/$(DEPDIR)/$(am__dirstamp)

bpf/libsim.a: $(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_DEPENDENCIES) $(EXTRA_bpf_libsim_a_DEPENDENCIES) bpf/$(am__dirstamp)
	$(AM_V_at)-rm -f bpf/libsim.a
	$(AM_V_AR)$(bpf_libsim_a_AR) bpf/libsim.a $(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) bpf/libsim.a

common/libcommon.a: $(common_libcommon_a_OBJECTS) $(common_libcommon_a_DEPENDENCIES) $(EXTRA_common_libcommon_a_DEPENDENCIES) common/$(am__dirstamp)
	$(AM_V_at)-rm -f common/libcommon.a
	$(AM_V_AR)$(common_libcommon_a_AR) common/libcommon.a $(common_libcommon_a_OBJECTS) $(common_libcommon_a_LIBADD)
	$(AM_V_at)$(RANLIB) common/libcommon.a
cr16/$(am__dirstamp):
	@$(MKDIR_P) cr16
	@: > cr16/$(am__dirstamp)
cr16/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) cr16/$(DEPDIR)
	@: > cr16/$(DEPDIR)/$(am__dirstamp)
cr16/modules.$(OBJEXT): cr16/$(am__dirstamp) \
	cr16/$(DEPDIR)/$(am__dirstamp)

cr16/libsim.a: $(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_DEPENDENCIES) $(EXTRA_cr16_libsim_a_DEPENDENCIES) cr16/$(am__dirstamp)
	$(AM_V_at)-rm -f cr16/libsim.a
	$(AM_V_AR)$(cr16_libsim_a_AR) cr16/libsim.a $(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) cr16/libsim.a
cris/$(am__dirstamp):
	@$(MKDIR_P) cris
	@: > cris/$(am__dirstamp)
cris/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) cris/$(DEPDIR)
	@: > cris/$(DEPDIR)/$(am__dirstamp)
cris/modules.$(OBJEXT): cris/$(am__dirstamp) \
	cris/$(DEPDIR)/$(am__dirstamp)

cris/libsim.a: $(cris_libsim_a_OBJECTS) $(cris_libsim_a_DEPENDENCIES) $(EXTRA_cris_libsim_a_DEPENDENCIES) cris/$(am__dirstamp)
	$(AM_V_at)-rm -f cris/libsim.a
	$(AM_V_AR)$(cris_libsim_a_AR) cris/libsim.a $(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) cris/libsim.a
d10v/$(am__dirstamp):
	@$(MKDIR_P) d10v
	@: > d10v/$(am__dirstamp)
d10v/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) d10v/$(DEPDIR)
	@: > d10v/$(DEPDIR)/$(am__dirstamp)
d10v/modules.$(OBJEXT): d10v/$(am__dirstamp) \
	d10v/$(DEPDIR)/$(am__dirstamp)

d10v/libsim.a: $(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_DEPENDENCIES) $(EXTRA_d10v_libsim_a_DEPENDENCIES) d10v/$(am__dirstamp)
	$(AM_V_at)-rm -f d10v/libsim.a
	$(AM_V_AR)$(d10v_libsim_a_AR) d10v/libsim.a $(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) d10v/libsim.a
erc32/$(am__dirstamp):
	@$(MKDIR_P) erc32
	@: > erc32/$(am__dirstamp)
erc32/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) erc32/$(DEPDIR)
	@: > erc32/$(DEPDIR)/$(am__dirstamp)
erc32/modules.$(OBJEXT): erc32/$(am__dirstamp) \
	erc32/$(DEPDIR)/$(am__dirstamp)

erc32/libsim.a: $(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_DEPENDENCIES) $(EXTRA_erc32_libsim_a_DEPENDENCIES) erc32/$(am__dirstamp)
	$(AM_V_at)-rm -f erc32/libsim.a
	$(AM_V_AR)$(erc32_libsim_a_AR) erc32/libsim.a $(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) erc32/libsim.a
example-synacor/$(am__dirstamp):
	@$(MKDIR_P) example-synacor
	@: > example-synacor/$(am__dirstamp)
example-synacor/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) example-synacor/$(DEPDIR)
	@: > example-synacor/$(DEPDIR)/$(am__dirstamp)
example-synacor/modules.$(OBJEXT): example-synacor/$(am__dirstamp) \
	example-synacor/$(DEPDIR)/$(am__dirstamp)

example-synacor/libsim.a: $(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_DEPENDENCIES) $(EXTRA_example_synacor_libsim_a_DEPENDENCIES) example-synacor/$(am__dirstamp)
	$(AM_V_at)-rm -f example-synacor/libsim.a
	$(AM_V_AR)$(example_synacor_libsim_a_AR) example-synacor/libsim.a $(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) example-synacor/libsim.a
frv/$(am__dirstamp):
	@$(MKDIR_P) frv
	@: > frv/$(am__dirstamp)
frv/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) frv/$(DEPDIR)
	@: > frv/$(DEPDIR)/$(am__dirstamp)
frv/modules.$(OBJEXT): frv/$(am__dirstamp) \
	frv/$(DEPDIR)/$(am__dirstamp)

frv/libsim.a: $(frv_libsim_a_OBJECTS) $(frv_libsim_a_DEPENDENCIES) $(EXTRA_frv_libsim_a_DEPENDENCIES) frv/$(am__dirstamp)
	$(AM_V_at)-rm -f frv/libsim.a
	$(AM_V_AR)$(frv_libsim_a_AR) frv/libsim.a $(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) frv/libsim.a
ft32/$(am__dirstamp):
	@$(MKDIR_P) ft32
	@: > ft32/$(am__dirstamp)
ft32/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) ft32/$(DEPDIR)
	@: > ft32/$(DEPDIR)/$(am__dirstamp)
ft32/modules.$(OBJEXT): ft32/$(am__dirstamp) \
	ft32/$(DEPDIR)/$(am__dirstamp)

ft32/libsim.a: $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_DEPENDENCIES) $(EXTRA_ft32_libsim_a_DEPENDENCIES) ft32/$(am__dirstamp)
	$(AM_V_at)-rm -f ft32/libsim.a
	$(AM_V_AR)$(ft32_libsim_a_AR) ft32/libsim.a $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) ft32/libsim.a
h8300/$(am__dirstamp):
	@$(MKDIR_P) h8300
	@: > h8300/$(am__dirstamp)
h8300/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) h8300/$(DEPDIR)
	@: > h8300/$(DEPDIR)/$(am__dirstamp)
h8300/modules.$(OBJEXT): h8300/$(am__dirstamp) \
	h8300/$(DEPDIR)/$(am__dirstamp)

h8300/libsim.a: $(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_DEPENDENCIES) $(EXTRA_h8300_libsim_a_DEPENDENCIES) h8300/$(am__dirstamp)
	$(AM_V_at)-rm -f h8300/libsim.a
	$(AM_V_AR)$(h8300_libsim_a_AR) h8300/libsim.a $(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) h8300/libsim.a
igen/$(am__dirstamp):
	@$(MKDIR_P) igen
	@: > igen/$(am__dirstamp)
igen/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) igen/$(DEPDIR)
	@: > igen/$(DEPDIR)/$(am__dirstamp)
igen/table.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/lf.$(OBJEXT): igen/$(am__dirstamp) igen/$(DEPDIR)/$(am__dirstamp)
igen/misc.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/filter_host.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/ld-decode.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/ld-cache.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/filter.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/ld-insn.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen-model.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen-itable.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen-icache.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen-semantics.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen-idecode.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen-support.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen-engine.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
igen/gen.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)
iq2000/$(am__dirstamp):
	@$(MKDIR_P) iq2000
	@: > iq2000/$(am__dirstamp)
iq2000/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) iq2000/$(DEPDIR)
	@: > iq2000/$(DEPDIR)/$(am__dirstamp)
iq2000/modules.$(OBJEXT): iq2000/$(am__dirstamp) \
	iq2000/$(DEPDIR)/$(am__dirstamp)

iq2000/libsim.a: $(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_DEPENDENCIES) $(EXTRA_iq2000_libsim_a_DEPENDENCIES) iq2000/$(am__dirstamp)
	$(AM_V_at)-rm -f iq2000/libsim.a
	$(AM_V_AR)$(iq2000_libsim_a_AR) iq2000/libsim.a $(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) iq2000/libsim.a
lm32/$(am__dirstamp):
	@$(MKDIR_P) lm32
	@: > lm32/$(am__dirstamp)
lm32/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) lm32/$(DEPDIR)
	@: > lm32/$(DEPDIR)/$(am__dirstamp)
lm32/modules.$(OBJEXT): lm32/$(am__dirstamp) \
	lm32/$(DEPDIR)/$(am__dirstamp)

lm32/libsim.a: $(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_DEPENDENCIES) $(EXTRA_lm32_libsim_a_DEPENDENCIES) lm32/$(am__dirstamp)
	$(AM_V_at)-rm -f lm32/libsim.a
	$(AM_V_AR)$(lm32_libsim_a_AR) lm32/libsim.a $(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) lm32/libsim.a
m32c/$(am__dirstamp):
	@$(MKDIR_P) m32c
	@: > m32c/$(am__dirstamp)
m32c/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) m32c/$(DEPDIR)
	@: > m32c/$(DEPDIR)/$(am__dirstamp)
m32c/modules.$(OBJEXT): m32c/$(am__dirstamp) \
	m32c/$(DEPDIR)/$(am__dirstamp)

m32c/libsim.a: $(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_DEPENDENCIES) $(EXTRA_m32c_libsim_a_DEPENDENCIES) m32c/$(am__dirstamp)
	$(AM_V_at)-rm -f m32c/libsim.a
	$(AM_V_AR)$(m32c_libsim_a_AR) m32c/libsim.a $(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) m32c/libsim.a
m32r/$(am__dirstamp):
	@$(MKDIR_P) m32r
	@: > m32r/$(am__dirstamp)
m32r/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) m32r/$(DEPDIR)
	@: > m32r/$(DEPDIR)/$(am__dirstamp)
m32r/modules.$(OBJEXT): m32r/$(am__dirstamp) \
	m32r/$(DEPDIR)/$(am__dirstamp)

m32r/libsim.a: $(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_DEPENDENCIES) $(EXTRA_m32r_libsim_a_DEPENDENCIES) m32r/$(am__dirstamp)
	$(AM_V_at)-rm -f m32r/libsim.a
	$(AM_V_AR)$(m32r_libsim_a_AR) m32r/libsim.a $(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) m32r/libsim.a
m68hc11/$(am__dirstamp):
	@$(MKDIR_P) m68hc11
	@: > m68hc11/$(am__dirstamp)
m68hc11/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) m68hc11/$(DEPDIR)
	@: > m68hc11/$(DEPDIR)/$(am__dirstamp)
m68hc11/modules.$(OBJEXT): m68hc11/$(am__dirstamp) \
	m68hc11/$(DEPDIR)/$(am__dirstamp)

m68hc11/libsim.a: $(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_DEPENDENCIES) $(EXTRA_m68hc11_libsim_a_DEPENDENCIES) m68hc11/$(am__dirstamp)
	$(AM_V_at)-rm -f m68hc11/libsim.a
	$(AM_V_AR)$(m68hc11_libsim_a_AR) m68hc11/libsim.a $(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) m68hc11/libsim.a
mcore/$(am__dirstamp):
	@$(MKDIR_P) mcore
	@: > mcore/$(am__dirstamp)
mcore/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) mcore/$(DEPDIR)
	@: > mcore/$(DEPDIR)/$(am__dirstamp)
mcore/modules.$(OBJEXT): mcore/$(am__dirstamp) \
	mcore/$(DEPDIR)/$(am__dirstamp)

mcore/libsim.a: $(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_DEPENDENCIES) $(EXTRA_mcore_libsim_a_DEPENDENCIES) mcore/$(am__dirstamp)
	$(AM_V_at)-rm -f mcore/libsim.a
	$(AM_V_AR)$(mcore_libsim_a_AR) mcore/libsim.a $(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) mcore/libsim.a
microblaze/$(am__dirstamp):
	@$(MKDIR_P) microblaze
	@: > microblaze/$(am__dirstamp)
microblaze/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) microblaze/$(DEPDIR)
	@: > microblaze/$(DEPDIR)/$(am__dirstamp)
microblaze/modules.$(OBJEXT): microblaze/$(am__dirstamp) \
	microblaze/$(DEPDIR)/$(am__dirstamp)

microblaze/libsim.a: $(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_DEPENDENCIES) $(EXTRA_microblaze_libsim_a_DEPENDENCIES) microblaze/$(am__dirstamp)
	$(AM_V_at)-rm -f microblaze/libsim.a
	$(AM_V_AR)$(microblaze_libsim_a_AR) microblaze/libsim.a $(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) microblaze/libsim.a
mips/$(am__dirstamp):
	@$(MKDIR_P) mips
	@: > mips/$(am__dirstamp)
mips/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) mips/$(DEPDIR)
	@: > mips/$(DEPDIR)/$(am__dirstamp)
mips/modules.$(OBJEXT): mips/$(am__dirstamp) \
	mips/$(DEPDIR)/$(am__dirstamp)

mips/libsim.a: $(mips_libsim_a_OBJECTS) $(mips_libsim_a_DEPENDENCIES) $(EXTRA_mips_libsim_a_DEPENDENCIES) mips/$(am__dirstamp)
	$(AM_V_at)-rm -f mips/libsim.a
	$(AM_V_AR)$(mips_libsim_a_AR) mips/libsim.a $(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) mips/libsim.a
mn10300/$(am__dirstamp):
	@$(MKDIR_P) mn10300
	@: > mn10300/$(am__dirstamp)
mn10300/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) mn10300/$(DEPDIR)
	@: > mn10300/$(DEPDIR)/$(am__dirstamp)
mn10300/modules.$(OBJEXT): mn10300/$(am__dirstamp) \
	mn10300/$(DEPDIR)/$(am__dirstamp)

mn10300/libsim.a: $(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_DEPENDENCIES) $(EXTRA_mn10300_libsim_a_DEPENDENCIES) mn10300/$(am__dirstamp)
	$(AM_V_at)-rm -f mn10300/libsim.a
	$(AM_V_AR)$(mn10300_libsim_a_AR) mn10300/libsim.a $(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) mn10300/libsim.a
moxie/$(am__dirstamp):
	@$(MKDIR_P) moxie
	@: > moxie/$(am__dirstamp)
moxie/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) moxie/$(DEPDIR)
	@: > moxie/$(DEPDIR)/$(am__dirstamp)
moxie/modules.$(OBJEXT): moxie/$(am__dirstamp) \
	moxie/$(DEPDIR)/$(am__dirstamp)

moxie/libsim.a: $(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_DEPENDENCIES) $(EXTRA_moxie_libsim_a_DEPENDENCIES) moxie/$(am__dirstamp)
	$(AM_V_at)-rm -f moxie/libsim.a
	$(AM_V_AR)$(moxie_libsim_a_AR) moxie/libsim.a $(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) moxie/libsim.a
msp430/$(am__dirstamp):
	@$(MKDIR_P) msp430
	@: > msp430/$(am__dirstamp)
msp430/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) msp430/$(DEPDIR)
	@: > msp430/$(DEPDIR)/$(am__dirstamp)
msp430/modules.$(OBJEXT): msp430/$(am__dirstamp) \
	msp430/$(DEPDIR)/$(am__dirstamp)

msp430/libsim.a: $(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_DEPENDENCIES) $(EXTRA_msp430_libsim_a_DEPENDENCIES) msp430/$(am__dirstamp)
	$(AM_V_at)-rm -f msp430/libsim.a
	$(AM_V_AR)$(msp430_libsim_a_AR) msp430/libsim.a $(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) msp430/libsim.a
or1k/$(am__dirstamp):
	@$(MKDIR_P) or1k
	@: > or1k/$(am__dirstamp)
or1k/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) or1k/$(DEPDIR)
	@: > or1k/$(DEPDIR)/$(am__dirstamp)
or1k/modules.$(OBJEXT): or1k/$(am__dirstamp) \
	or1k/$(DEPDIR)/$(am__dirstamp)

or1k/libsim.a: $(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_DEPENDENCIES) $(EXTRA_or1k_libsim_a_DEPENDENCIES) or1k/$(am__dirstamp)
	$(AM_V_at)-rm -f or1k/libsim.a
	$(AM_V_AR)$(or1k_libsim_a_AR) or1k/libsim.a $(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) or1k/libsim.a
ppc/$(am__dirstamp):
	@$(MKDIR_P) ppc
	@: > ppc/$(am__dirstamp)
ppc/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) ppc/$(DEPDIR)
	@: > ppc/$(DEPDIR)/$(am__dirstamp)
ppc/table.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)/$(am__dirstamp)
ppc/lf-ppc.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/dumpf.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)/$(am__dirstamp)
ppc/ld-decode.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/ld-cache.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/filter-ppc.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/ld-insn.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/gen-model.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/gen-itable.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/gen-icache.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/gen-semantics.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/gen-idecode.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)
ppc/gen-support.$(OBJEXT): ppc/$(am__dirstamp) \
	ppc/$(DEPDIR)/$(am__dirstamp)

@SIM_ENABLE_ARCH_ppc_FALSE@ppc/libigen.a: $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_DEPENDENCIES) $(EXTRA_ppc_libigen_a_DEPENDENCIES) ppc/$(am__dirstamp)
@SIM_ENABLE_ARCH_ppc_FALSE@	$(AM_V_at)-rm -f ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_FALSE@	$(AM_V_AR)$(ppc_libigen_a_AR) ppc/libigen.a $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_LIBADD)
@SIM_ENABLE_ARCH_ppc_FALSE@	$(AM_V_at)$(RANLIB) ppc/libigen.a

ppc/libsim.a: $(ppc_libsim_a_OBJECTS) $(ppc_libsim_a_DEPENDENCIES) $(EXTRA_ppc_libsim_a_DEPENDENCIES) ppc/$(am__dirstamp)
	$(AM_V_at)-rm -f ppc/libsim.a
	$(AM_V_AR)$(ppc_libsim_a_AR) ppc/libsim.a $(ppc_libsim_a_OBJECTS) $(ppc_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) ppc/libsim.a
pru/$(am__dirstamp):
	@$(MKDIR_P) pru
	@: > pru/$(am__dirstamp)
pru/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) pru/$(DEPDIR)
	@: > pru/$(DEPDIR)/$(am__dirstamp)
pru/modules.$(OBJEXT): pru/$(am__dirstamp) \
	pru/$(DEPDIR)/$(am__dirstamp)

pru/libsim.a: $(pru_libsim_a_OBJECTS) $(pru_libsim_a_DEPENDENCIES) $(EXTRA_pru_libsim_a_DEPENDENCIES) pru/$(am__dirstamp)
	$(AM_V_at)-rm -f pru/libsim.a
	$(AM_V_AR)$(pru_libsim_a_AR) pru/libsim.a $(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) pru/libsim.a
riscv/$(am__dirstamp):
	@$(MKDIR_P) riscv
	@: > riscv/$(am__dirstamp)
riscv/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) riscv/$(DEPDIR)
	@: > riscv/$(DEPDIR)/$(am__dirstamp)
riscv/modules.$(OBJEXT): riscv/$(am__dirstamp) \
	riscv/$(DEPDIR)/$(am__dirstamp)

riscv/libsim.a: $(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_DEPENDENCIES) $(EXTRA_riscv_libsim_a_DEPENDENCIES) riscv/$(am__dirstamp)
	$(AM_V_at)-rm -f riscv/libsim.a
	$(AM_V_AR)$(riscv_libsim_a_AR) riscv/libsim.a $(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) riscv/libsim.a
rl78/$(am__dirstamp):
	@$(MKDIR_P) rl78
	@: > rl78/$(am__dirstamp)
rl78/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) rl78/$(DEPDIR)
	@: > rl78/$(DEPDIR)/$(am__dirstamp)
rl78/modules.$(OBJEXT): rl78/$(am__dirstamp) \
	rl78/$(DEPDIR)/$(am__dirstamp)

rl78/libsim.a: $(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_DEPENDENCIES) $(EXTRA_rl78_libsim_a_DEPENDENCIES) rl78/$(am__dirstamp)
	$(AM_V_at)-rm -f rl78/libsim.a
	$(AM_V_AR)$(rl78_libsim_a_AR) rl78/libsim.a $(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) rl78/libsim.a
rx/$(am__dirstamp):
	@$(MKDIR_P) rx
	@: > rx/$(am__dirstamp)
rx/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) rx/$(DEPDIR)
	@: > rx/$(DEPDIR)/$(am__dirstamp)
rx/modules.$(OBJEXT): rx/$(am__dirstamp) rx/$(DEPDIR)/$(am__dirstamp)

rx/libsim.a: $(rx_libsim_a_OBJECTS) $(rx_libsim_a_DEPENDENCIES) $(EXTRA_rx_libsim_a_DEPENDENCIES) rx/$(am__dirstamp)
	$(AM_V_at)-rm -f rx/libsim.a
	$(AM_V_AR)$(rx_libsim_a_AR) rx/libsim.a $(rx_libsim_a_OBJECTS) $(rx_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) rx/libsim.a
sh/$(am__dirstamp):
	@$(MKDIR_P) sh
	@: > sh/$(am__dirstamp)
sh/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) sh/$(DEPDIR)
	@: > sh/$(DEPDIR)/$(am__dirstamp)
sh/modules.$(OBJEXT): sh/$(am__dirstamp) sh/$(DEPDIR)/$(am__dirstamp)

sh/libsim.a: $(sh_libsim_a_OBJECTS) $(sh_libsim_a_DEPENDENCIES) $(EXTRA_sh_libsim_a_DEPENDENCIES) sh/$(am__dirstamp)
	$(AM_V_at)-rm -f sh/libsim.a
	$(AM_V_AR)$(sh_libsim_a_AR) sh/libsim.a $(sh_libsim_a_OBJECTS) $(sh_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) sh/libsim.a
v850/$(am__dirstamp):
	@$(MKDIR_P) v850
	@: > v850/$(am__dirstamp)
v850/$(DEPDIR)/$(am__dirstamp):
	@$(MKDIR_P) v850/$(DEPDIR)
	@: > v850/$(DEPDIR)/$(am__dirstamp)
v850/modules.$(OBJEXT): v850/$(am__dirstamp) \
	v850/$(DEPDIR)/$(am__dirstamp)

v850/libsim.a: $(v850_libsim_a_OBJECTS) $(v850_libsim_a_DEPENDENCIES) $(EXTRA_v850_libsim_a_DEPENDENCIES) v850/$(am__dirstamp)
	$(AM_V_at)-rm -f v850/libsim.a
	$(AM_V_AR)$(v850_libsim_a_AR) v850/libsim.a $(v850_libsim_a_OBJECTS) $(v850_libsim_a_LIBADD)
	$(AM_V_at)$(RANLIB) v850/libsim.a

clean-checkPROGRAMS:
	@list='$(check_PROGRAMS)'; test -n "$$list" || exit 0; \
	echo " rm -f" $$list; \
	rm -f $$list || exit $$?; \
	test -n "$(EXEEXT)" || exit 0; \
	list=`for p in $$list; do echo "$$p"; done | sed 's/$(EXEEXT)$$//'`; \
	echo " rm -f" $$list; \
	rm -f $$list

clean-noinstPROGRAMS:
	@list='$(noinst_PROGRAMS)'; test -n "$$list" || exit 0; \
	echo " rm -f" $$list; \
	rm -f $$list || exit $$?; \
	test -n "$(EXEEXT)" || exit 0; \
	list=`for p in $$list; do echo "$$p"; done | sed 's/$(EXEEXT)$$//'`; \
	echo " rm -f" $$list; \
	rm -f $$list

aarch64/run$(EXEEXT): $(aarch64_run_OBJECTS) $(aarch64_run_DEPENDENCIES) $(EXTRA_aarch64_run_DEPENDENCIES) aarch64/$(am__dirstamp)
	@rm -f aarch64/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(aarch64_run_OBJECTS) $(aarch64_run_LDADD) $(LIBS)

arm/run$(EXEEXT): $(arm_run_OBJECTS) $(arm_run_DEPENDENCIES) $(EXTRA_arm_run_DEPENDENCIES) arm/$(am__dirstamp)
	@rm -f arm/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(arm_run_OBJECTS) $(arm_run_LDADD) $(LIBS)

avr/run$(EXEEXT): $(avr_run_OBJECTS) $(avr_run_DEPENDENCIES) $(EXTRA_avr_run_DEPENDENCIES) avr/$(am__dirstamp)
	@rm -f avr/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(avr_run_OBJECTS) $(avr_run_LDADD) $(LIBS)

bfin/run$(EXEEXT): $(bfin_run_OBJECTS) $(bfin_run_DEPENDENCIES) $(EXTRA_bfin_run_DEPENDENCIES) bfin/$(am__dirstamp)
	@rm -f bfin/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(bfin_run_OBJECTS) $(bfin_run_LDADD) $(LIBS)

bpf/run$(EXEEXT): $(bpf_run_OBJECTS) $(bpf_run_DEPENDENCIES) $(EXTRA_bpf_run_DEPENDENCIES) bpf/$(am__dirstamp)
	@rm -f bpf/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(bpf_run_OBJECTS) $(bpf_run_LDADD) $(LIBS)
cr16/gencode.$(OBJEXT): cr16/$(am__dirstamp) \
	cr16/$(DEPDIR)/$(am__dirstamp)

@SIM_ENABLE_ARCH_cr16_FALSE@cr16/gencode$(EXEEXT): $(cr16_gencode_OBJECTS) $(cr16_gencode_DEPENDENCIES) $(EXTRA_cr16_gencode_DEPENDENCIES) cr16/$(am__dirstamp)
@SIM_ENABLE_ARCH_cr16_FALSE@	@rm -f cr16/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_FALSE@	$(AM_V_CCLD)$(LINK) $(cr16_gencode_OBJECTS) $(cr16_gencode_LDADD) $(LIBS)

cr16/run$(EXEEXT): $(cr16_run_OBJECTS) $(cr16_run_DEPENDENCIES) $(EXTRA_cr16_run_DEPENDENCIES) cr16/$(am__dirstamp)
	@rm -f cr16/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(cr16_run_OBJECTS) $(cr16_run_LDADD) $(LIBS)

cris/run$(EXEEXT): $(cris_run_OBJECTS) $(cris_run_DEPENDENCIES) $(EXTRA_cris_run_DEPENDENCIES) cris/$(am__dirstamp)
	@rm -f cris/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(cris_run_OBJECTS) $(cris_run_LDADD) $(LIBS)
cris/rvdummy.$(OBJEXT): cris/$(am__dirstamp) \
	cris/$(DEPDIR)/$(am__dirstamp)

cris/rvdummy$(EXEEXT): $(cris_rvdummy_OBJECTS) $(cris_rvdummy_DEPENDENCIES) $(EXTRA_cris_rvdummy_DEPENDENCIES) cris/$(am__dirstamp)
	@rm -f cris/rvdummy$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(cris_rvdummy_OBJECTS) $(cris_rvdummy_LDADD) $(LIBS)
d10v/gencode.$(OBJEXT): d10v/$(am__dirstamp) \
	d10v/$(DEPDIR)/$(am__dirstamp)

@SIM_ENABLE_ARCH_d10v_FALSE@d10v/gencode$(EXEEXT): $(d10v_gencode_OBJECTS) $(d10v_gencode_DEPENDENCIES) $(EXTRA_d10v_gencode_DEPENDENCIES) d10v/$(am__dirstamp)
@SIM_ENABLE_ARCH_d10v_FALSE@	@rm -f d10v/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_FALSE@	$(AM_V_CCLD)$(LINK) $(d10v_gencode_OBJECTS) $(d10v_gencode_LDADD) $(LIBS)

d10v/run$(EXEEXT): $(d10v_run_OBJECTS) $(d10v_run_DEPENDENCIES) $(EXTRA_d10v_run_DEPENDENCIES) d10v/$(am__dirstamp)
	@rm -f d10v/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(d10v_run_OBJECTS) $(d10v_run_LDADD) $(LIBS)

erc32/run$(EXEEXT): $(erc32_run_OBJECTS) $(erc32_run_DEPENDENCIES) $(EXTRA_erc32_run_DEPENDENCIES) erc32/$(am__dirstamp)
	@rm -f erc32/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(erc32_run_OBJECTS) $(erc32_run_LDADD) $(LIBS)
erc32/sis.$(OBJEXT): erc32/$(am__dirstamp) \
	erc32/$(DEPDIR)/$(am__dirstamp)

@SIM_ENABLE_ARCH_erc32_FALSE@erc32/sis$(EXEEXT): $(erc32_sis_OBJECTS) $(erc32_sis_DEPENDENCIES) $(EXTRA_erc32_sis_DEPENDENCIES) erc32/$(am__dirstamp)
@SIM_ENABLE_ARCH_erc32_FALSE@	@rm -f erc32/sis$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_FALSE@	$(AM_V_CCLD)$(LINK) $(erc32_sis_OBJECTS) $(erc32_sis_LDADD) $(LIBS)

example-synacor/run$(EXEEXT): $(example_synacor_run_OBJECTS) $(example_synacor_run_DEPENDENCIES) $(EXTRA_example_synacor_run_DEPENDENCIES) example-synacor/$(am__dirstamp)
	@rm -f example-synacor/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(example_synacor_run_OBJECTS) $(example_synacor_run_LDADD) $(LIBS)

frv/run$(EXEEXT): $(frv_run_OBJECTS) $(frv_run_DEPENDENCIES) $(EXTRA_frv_run_DEPENDENCIES) frv/$(am__dirstamp)
	@rm -f frv/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(frv_run_OBJECTS) $(frv_run_LDADD) $(LIBS)

ft32/run$(EXEEXT): $(ft32_run_OBJECTS) $(ft32_run_DEPENDENCIES) $(EXTRA_ft32_run_DEPENDENCIES) ft32/$(am__dirstamp)
	@rm -f ft32/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(ft32_run_OBJECTS) $(ft32_run_LDADD) $(LIBS)

h8300/run$(EXEEXT): $(h8300_run_OBJECTS) $(h8300_run_DEPENDENCIES) $(EXTRA_h8300_run_DEPENDENCIES) h8300/$(am__dirstamp)
	@rm -f h8300/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(h8300_run_OBJECTS) $(h8300_run_LDADD) $(LIBS)

igen/filter$(EXEEXT): $(igen_filter_OBJECTS) $(igen_filter_DEPENDENCIES) $(EXTRA_igen_filter_DEPENDENCIES) igen/$(am__dirstamp)
	@rm -f igen/filter$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(igen_filter_OBJECTS) $(igen_filter_LDADD) $(LIBS)

igen/gen$(EXEEXT): $(igen_gen_OBJECTS) $(igen_gen_DEPENDENCIES) $(EXTRA_igen_gen_DEPENDENCIES) igen/$(am__dirstamp)
	@rm -f igen/gen$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(igen_gen_OBJECTS) $(igen_gen_LDADD) $(LIBS)
igen/igen.$(OBJEXT): igen/$(am__dirstamp) \
	igen/$(DEPDIR)/$(am__dirstamp)

igen/ld-cache$(EXEEXT): $(igen_ld_cache_OBJECTS) $(igen_ld_cache_DEPENDENCIES) $(EXTRA_igen_ld_cache_DEPENDENCIES) igen/$(am__dirstamp)
	@rm -f igen/ld-cache$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(igen_ld_cache_OBJECTS) $(igen_ld_cache_LDADD) $(LIBS)

igen/ld-decode$(EXEEXT): $(igen_ld_decode_OBJECTS) $(igen_ld_decode_DEPENDENCIES) $(EXTRA_igen_ld_decode_DEPENDENCIES) igen/$(am__dirstamp)
	@rm -f igen/ld-decode$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(igen_ld_decode_OBJECTS) $(igen_ld_decode_LDADD) $(LIBS)

igen/ld-insn$(EXEEXT): $(igen_ld_insn_OBJECTS) $(igen_ld_insn_DEPENDENCIES) $(EXTRA_igen_ld_insn_DEPENDENCIES) igen/$(am__dirstamp)
	@rm -f igen/ld-insn$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(igen_ld_insn_OBJECTS) $(igen_ld_insn_LDADD) $(LIBS)

igen/table$(EXEEXT): $(igen_table_OBJECTS) $(igen_table_DEPENDENCIES) $(EXTRA_igen_table_DEPENDENCIES) igen/$(am__dirstamp)
	@rm -f igen/table$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(igen_table_OBJECTS) $(igen_table_LDADD) $(LIBS)

iq2000/run$(EXEEXT): $(iq2000_run_OBJECTS) $(iq2000_run_DEPENDENCIES) $(EXTRA_iq2000_run_DEPENDENCIES) iq2000/$(am__dirstamp)
	@rm -f iq2000/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(iq2000_run_OBJECTS) $(iq2000_run_LDADD) $(LIBS)

lm32/run$(EXEEXT): $(lm32_run_OBJECTS) $(lm32_run_DEPENDENCIES) $(EXTRA_lm32_run_DEPENDENCIES) lm32/$(am__dirstamp)
	@rm -f lm32/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(lm32_run_OBJECTS) $(lm32_run_LDADD) $(LIBS)
m32c/opc2c.$(OBJEXT): m32c/$(am__dirstamp) \
	m32c/$(DEPDIR)/$(am__dirstamp)

@SIM_ENABLE_ARCH_m32c_FALSE@m32c/opc2c$(EXEEXT): $(m32c_opc2c_OBJECTS) $(m32c_opc2c_DEPENDENCIES) $(EXTRA_m32c_opc2c_DEPENDENCIES) m32c/$(am__dirstamp)
@SIM_ENABLE_ARCH_m32c_FALSE@	@rm -f m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_FALSE@	$(AM_V_CCLD)$(LINK) $(m32c_opc2c_OBJECTS) $(m32c_opc2c_LDADD) $(LIBS)

m32c/run$(EXEEXT): $(m32c_run_OBJECTS) $(m32c_run_DEPENDENCIES) $(EXTRA_m32c_run_DEPENDENCIES) m32c/$(am__dirstamp)
	@rm -f m32c/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(m32c_run_OBJECTS) $(m32c_run_LDADD) $(LIBS)

m32r/run$(EXEEXT): $(m32r_run_OBJECTS) $(m32r_run_DEPENDENCIES) $(EXTRA_m32r_run_DEPENDENCIES) m32r/$(am__dirstamp)
	@rm -f m32r/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(m32r_run_OBJECTS) $(m32r_run_LDADD) $(LIBS)
m68hc11/gencode.$(OBJEXT): m68hc11/$(am__dirstamp) \
	m68hc11/$(DEPDIR)/$(am__dirstamp)

@SIM_ENABLE_ARCH_m68hc11_FALSE@m68hc11/gencode$(EXEEXT): $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_DEPENDENCIES) $(EXTRA_m68hc11_gencode_DEPENDENCIES) m68hc11/$(am__dirstamp)
@SIM_ENABLE_ARCH_m68hc11_FALSE@	@rm -f m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_FALSE@	$(AM_V_CCLD)$(LINK) $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_LDADD) $(LIBS)

m68hc11/run$(EXEEXT): $(m68hc11_run_OBJECTS) $(m68hc11_run_DEPENDENCIES) $(EXTRA_m68hc11_run_DEPENDENCIES) m68hc11/$(am__dirstamp)
	@rm -f m68hc11/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(m68hc11_run_OBJECTS) $(m68hc11_run_LDADD) $(LIBS)

mcore/run$(EXEEXT): $(mcore_run_OBJECTS) $(mcore_run_DEPENDENCIES) $(EXTRA_mcore_run_DEPENDENCIES) mcore/$(am__dirstamp)
	@rm -f mcore/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(mcore_run_OBJECTS) $(mcore_run_LDADD) $(LIBS)

microblaze/run$(EXEEXT): $(microblaze_run_OBJECTS) $(microblaze_run_DEPENDENCIES) $(EXTRA_microblaze_run_DEPENDENCIES) microblaze/$(am__dirstamp)
	@rm -f microblaze/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(microblaze_run_OBJECTS) $(microblaze_run_LDADD) $(LIBS)

mips/run$(EXEEXT): $(mips_run_OBJECTS) $(mips_run_DEPENDENCIES) $(EXTRA_mips_run_DEPENDENCIES) mips/$(am__dirstamp)
	@rm -f mips/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(mips_run_OBJECTS) $(mips_run_LDADD) $(LIBS)

mn10300/run$(EXEEXT): $(mn10300_run_OBJECTS) $(mn10300_run_DEPENDENCIES) $(EXTRA_mn10300_run_DEPENDENCIES) mn10300/$(am__dirstamp)
	@rm -f mn10300/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(mn10300_run_OBJECTS) $(mn10300_run_LDADD) $(LIBS)

moxie/run$(EXEEXT): $(moxie_run_OBJECTS) $(moxie_run_DEPENDENCIES) $(EXTRA_moxie_run_DEPENDENCIES) moxie/$(am__dirstamp)
	@rm -f moxie/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(moxie_run_OBJECTS) $(moxie_run_LDADD) $(LIBS)

msp430/run$(EXEEXT): $(msp430_run_OBJECTS) $(msp430_run_DEPENDENCIES) $(EXTRA_msp430_run_DEPENDENCIES) msp430/$(am__dirstamp)
	@rm -f msp430/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(msp430_run_OBJECTS) $(msp430_run_LDADD) $(LIBS)

or1k/run$(EXEEXT): $(or1k_run_OBJECTS) $(or1k_run_DEPENDENCIES) $(EXTRA_or1k_run_DEPENDENCIES) or1k/$(am__dirstamp)
	@rm -f or1k/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(or1k_run_OBJECTS) $(or1k_run_LDADD) $(LIBS)
ppc/igen.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)/$(am__dirstamp)

@SIM_ENABLE_ARCH_ppc_FALSE@ppc/igen$(EXEEXT): $(ppc_igen_OBJECTS) $(ppc_igen_DEPENDENCIES) $(EXTRA_ppc_igen_DEPENDENCIES) ppc/$(am__dirstamp)
@SIM_ENABLE_ARCH_ppc_FALSE@	@rm -f ppc/igen$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_FALSE@	$(AM_V_CCLD)$(LINK) $(ppc_igen_OBJECTS) $(ppc_igen_LDADD) $(LIBS)

ppc/ld-cache$(EXEEXT): $(ppc_ld_cache_OBJECTS) $(ppc_ld_cache_DEPENDENCIES) $(EXTRA_ppc_ld_cache_DEPENDENCIES) ppc/$(am__dirstamp)
	@rm -f ppc/ld-cache$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(ppc_ld_cache_OBJECTS) $(ppc_ld_cache_LDADD) $(LIBS)

ppc/ld-decode$(EXEEXT): $(ppc_ld_decode_OBJECTS) $(ppc_ld_decode_DEPENDENCIES) $(EXTRA_ppc_ld_decode_DEPENDENCIES) ppc/$(am__dirstamp)
	@rm -f ppc/ld-decode$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(ppc_ld_decode_OBJECTS) $(ppc_ld_decode_LDADD) $(LIBS)

ppc/ld-insn$(EXEEXT): $(ppc_ld_insn_OBJECTS) $(ppc_ld_insn_DEPENDENCIES) $(EXTRA_ppc_ld_insn_DEPENDENCIES) ppc/$(am__dirstamp)
	@rm -f ppc/ld-insn$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(ppc_ld_insn_OBJECTS) $(ppc_ld_insn_LDADD) $(LIBS)
ppc/main.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)/$(am__dirstamp)

ppc/run$(EXEEXT): $(ppc_run_OBJECTS) $(ppc_run_DEPENDENCIES) $(EXTRA_ppc_run_DEPENDENCIES) ppc/$(am__dirstamp)
	@rm -f ppc/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(ppc_run_OBJECTS) $(ppc_run_LDADD) $(LIBS)

pru/run$(EXEEXT): $(pru_run_OBJECTS) $(pru_run_DEPENDENCIES) $(EXTRA_pru_run_DEPENDENCIES) pru/$(am__dirstamp)
	@rm -f pru/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(pru_run_OBJECTS) $(pru_run_LDADD) $(LIBS)

riscv/run$(EXEEXT): $(riscv_run_OBJECTS) $(riscv_run_DEPENDENCIES) $(EXTRA_riscv_run_DEPENDENCIES) riscv/$(am__dirstamp)
	@rm -f riscv/run$(EXEEXT)
	$(AM_V_CCLD)$(LINK) $(riscv_run_OBJECTS) $(riscv_run_LDADD) $(LIBS)