)]}'
{
  "commit": "e87ff6724fe32ecff11fc36a19a09ab8fbc66c13",
  "tree": "823fcf67a24355b4f02e6455769a224a5a05a1d7",
  "parents": [
    "cbd11b8818335007cf960e0cecc4dec445f80327"
  ],
  "author": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:13 2023 +0100"
  },
  "committer": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:13 2023 +0100"
  },
  "message": "aarch64: Add the SME2 ADD and SUB instructions\n\nAdd support for the SME2 ADD. SUB, FADD and FSUB instructions.\nSUB and FSUB have the same form as ADD and FADD, except that\nADD also has a 2-operand accumulating form.\n\nThe 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the\n64-bit FADD/FSUB instructions require FEAT_SME_F64F64.\n\nThese are the first instructions to have tied register list\noperands, as opposed to tied single registers.\n\nThe parse_operands change prevents unsuffixed Z registers (width\u003d\u003d-1)\nfrom being treated as though they had an Advanced SIMD-style suffix\n(.4s etc.).  It means that:\n\n  Error: expected element type rather than vector type at operand 2 -- `add za\\.s\\[w8,0\\],{z0-z1}\u0027\n\nbecomes:\n\n  Error: missing type suffix at operand 2 -- `add za\\.s\\[w8,0\\],{z0-z1}\u0027\n",
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