)]}'
{
  "commit": "e9f7ba21f08a264f813140eb6221e9d9670dc12f",
  "tree": "da6e290e6ecd9ee120d1e87acbc3a2a877252f60",
  "parents": [
    "5edf42b635a375f7bf79e2079529eeb869129cbe"
  ],
  "author": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Sat Aug 27 00:10:58 2022 +0000"
  },
  "committer": {
    "name": "Nelson Chu",
    "email": "nelson@rivosinc.com",
    "time": "Fri Sep 02 09:40:04 2022 +0800"
  },
  "message": "RISC-V: Add address printer tests with ADDIW\n\nAddress sequences involving ADDIW/C.ADDIW instructions require special\nhandling to sign-extend lower 32-bits of the original result.\n\nThis commit tests whether this sign-extension works.\n\ngas/ChangeLog:\n\n\t* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address\n\tcomputation with sign extension as used in ADDIW/C.ADDIW.\n\t* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.\n\t* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.\n\ngas/ChangeLog:\n\n\t* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.\n\t* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.\n\t* testsuite/gas/riscv/dis-addr-addiw.s: New test.\n",
  "tree_diff": [
    {
      "type": "add",
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3cd9d4e3805255c372947f91f12e38561373df81",
      "new_mode": 33188,
      "new_path": "gas/testsuite/gas/riscv/dis-addr-addiw-a.d"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2c68d6b6e5f72b6064c43ccc07ebc64ec1d70d1f",
      "new_mode": 33188,
      "new_path": "gas/testsuite/gas/riscv/dis-addr-addiw-b.d"
    },
    {
      "type": "add",
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      "new_id": "7c878f86dd6208dc184379722659f4d15d7d83c4",
      "new_mode": 33188,
      "new_path": "gas/testsuite/gas/riscv/dis-addr-addiw.s"
    }
  ]
}