)]}'
{
  "commit": "f3f6c0df60c4e8a6c3409db4f23f2cdec5a9d41c",
  "tree": "befa3e9332d98f77d7168b4b0a11f3a09909e1e1",
  "parents": [
    "f0d70d8ee63b6f6a59cf4a10268f546b0bc80777"
  ],
  "author": {
    "name": "Victor Do Nascimento",
    "email": "victor.donascimento@arm.com",
    "time": "Tue Sep 12 13:10:14 2023 +0100"
  },
  "committer": {
    "name": "Victor Do Nascimento",
    "email": "victor.donascimento@arm.com",
    "time": "Tue Nov 07 21:54:19 2023 +0000"
  },
  "message": "aarch64: Add LSE128 instructions\n\nImplement, together with the necessary tests, the following new LSE128\natomic instructions:\n\n  * Atomic bit clear on quadword in memory (ldclrp{a|l|al});\n  * Atomic bit set on quadword in memory (ldsetp{a|l|al});\n  * Swap quadword in memory (swpp{a|l|al});\n\ngas/ChangeLog:\n\n\t* testsuite/gas/aarch64/lse128-atomic.d: New.\n\t* testsuite/gas/aarch64/lse128-atomic.s: Likewise.\n\nopcodes/ChangeLog:\n\n\t* aarch64-tbl.h (ldclrp): new _LSE128_INSN entry.\n\t(ldclrpa):  Likewise.\n\t(ldclrpal): Likewise.\n\t(ldclrpl): Likewise.\n\t(ldsetp): Likewise.\n\t(ldsetpa): Likewise.\n\t(ldsetpal): Likewise.\n\t(ldsetpl): Likewise.\n\t(swpp): Likewise.\n\t(swppa): Likewise.\n\t(swppal): Likewise.\n\t(swppl): Likewise.\n\t* aarch64-asm-2.c: Regenerate.\n\t* aarch64-dis-2.c: Likewise.\n\t* aarch64-opc-2.c: Likewise.\n",
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