)]}'
{
  "commit": "f56532cc17868e2c7e765bfd78322157048ff6ec",
  "tree": "f15c88fd5a6bd83d12be0503c56b26a92412caba",
  "parents": [
    "a95fb4e34650382a4eb0856035129f2a2f0aaf4c"
  ],
  "author": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Wed Jan 11 10:31:43 2023 +0100"
  },
  "committer": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Wed Jan 11 10:31:43 2023 +0100"
  },
  "message": "gas/RISC-V: adjust assembler for opcode table re-ordering\n\nPR gas/29940\n\nWith the single-operand JAL entry now sitting ahead of the two-operand\none, the parsing of a two-operand insn would first try to parse an \u0027a\u0027-\nstyle operand, resulting in the insertion of bogus (and otherwise\nunused) undefined symbols in the symbol table, having register names.\nSince \u0027a\u0027 is used as 1st operand only with J and JAL, and since JAL is\nthe only insn _also_ allowing for a register as 1st operand (and then\nthere being a 2nd one), special case this parsing aspect right there.\n\nReviewed-by: Palmer Dabbelt \u003cpalmer@rivosinc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2dc41768ce375cdac9b588334febfbbcb10d7b97",
      "old_mode": 33188,
      "old_path": "gas/config/tc-riscv.c",
      "new_id": "6793b6448b3705e00448e9ea7db98d492d2cd4dd",
      "new_mode": 33188,
      "new_path": "gas/config/tc-riscv.c"
    }
  ]
}