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v850/.gdbinit example-synacor/.gdbinit .gdbinit
CONFIG_CLEAN_VPATH_FILES =
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ARFLAGS = cru
AM_V_AR = $(am__v_AR_@AM_V@)
am__v_AR_ = $(am__v_AR_@AM_DEFAULT_V@)
am__v_AR_0 = @echo " AR " $@;
am__v_AR_1 =
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@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_DEPENDENCIES = \
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@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/interp.o \
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common/sim-load.$(OBJEXT) common/sim-signal.$(OBJEXT) \
common/syscall.$(OBJEXT) common/target-newlib-errno.$(OBJEXT) \
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@SIM_ENABLE_ARCH_arm_TRUE@ arm/arminit.o arm/armos.o \
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arm_libsim_a_OBJECTS = $(am_arm_libsim_a_OBJECTS) \
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d10v_libsim_a_AR = $(AR) $(ARFLAGS)
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erc32_libsim_a_AR = $(AR) $(ARFLAGS)
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example_synacor_libsim_a_AR = $(AR) $(ARFLAGS)
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example_synacor_libsim_a_OBJECTS = \
$(am_example_synacor_libsim_a_OBJECTS) \
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frv_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_DEPENDENCIES = $(patsubst \
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igen/misc.$(OBJEXT) igen/filter_host.$(OBJEXT) \
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igen/filter.$(OBJEXT) igen/ld-insn.$(OBJEXT) \
igen/gen-model.$(OBJEXT) igen/gen-itable.$(OBJEXT) \
igen/gen-icache.$(OBJEXT) igen/gen-semantics.$(OBJEXT) \
igen/gen-idecode.$(OBJEXT) igen/gen-support.$(OBJEXT) \
igen/gen-engine.$(OBJEXT) igen/gen.$(OBJEXT)
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@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.$(OBJEXT)
m32r_libsim_a_OBJECTS = $(am_m32r_libsim_a_OBJECTS) \
$(nodist_m32r_libsim_a_OBJECTS)
m68hc11_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_DEPENDENCIES = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11_sim.o $(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o
@SIM_ENABLE_ARCH_m68hc11_TRUE@am_m68hc11_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_m68hc11_TRUE@nodist_m68hc11_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.$(OBJEXT)
m68hc11_libsim_a_OBJECTS = $(am_m68hc11_libsim_a_OBJECTS) \
$(nodist_m68hc11_libsim_a_OBJECTS)
mcore_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_DEPENDENCIES = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o $(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@ %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@ %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/sim-resume.o
@SIM_ENABLE_ARCH_mcore_TRUE@am_mcore_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_mcore_TRUE@nodist_mcore_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.$(OBJEXT)
mcore_libsim_a_OBJECTS = $(am_mcore_libsim_a_OBJECTS) \
$(nodist_mcore_libsim_a_OBJECTS)
microblaze_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_DEPENDENCIES = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_microblaze_TRUE@ %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_microblaze_TRUE@ %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o
@SIM_ENABLE_ARCH_microblaze_TRUE@am_microblaze_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_microblaze_TRUE@nodist_microblaze_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.$(OBJEXT)
microblaze_libsim_a_OBJECTS = $(am_microblaze_libsim_a_OBJECTS) \
$(nodist_microblaze_libsim_a_OBJECTS)
mips_libsim_a_AR = $(AR) $(ARFLAGS)
am__DEPENDENCIES_1 =
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@ %,mips/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@ %,mips/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@ %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/cp1.o mips/dsp.o mips/mdmx.o \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-main.o mips/sim-resume.o
@SIM_ENABLE_ARCH_mips_TRUE@am_mips_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.$(OBJEXT)
mips_libsim_a_OBJECTS = $(am_mips_libsim_a_OBJECTS) \
$(nodist_mips_libsim_a_OBJECTS)
mn10300_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_DEPENDENCIES = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.o mn10300/irun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.o $(patsubst \
@SIM_ENABLE_ARCH_mn10300_TRUE@ %,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_mn10300_TRUE@ %,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_mn10300_TRUE@ %,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/interp.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/op_utils.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/sim-resume.o
@SIM_ENABLE_ARCH_mn10300_TRUE@am_mn10300_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_mn10300_TRUE@nodist_mn10300_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/modules.$(OBJEXT)
mn10300_libsim_a_OBJECTS = $(am_mn10300_libsim_a_OBJECTS) \
$(nodist_mn10300_libsim_a_OBJECTS)
moxie_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_moxie_TRUE@ %,moxie/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_moxie_TRUE@ %,moxie/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/interp.o moxie/sim-resume.o
@SIM_ENABLE_ARCH_moxie_TRUE@am_moxie_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_moxie_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_moxie_TRUE@nodist_moxie_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/modules.$(OBJEXT)
moxie_libsim_a_OBJECTS = $(am_moxie_libsim_a_OBJECTS) \
$(nodist_moxie_libsim_a_OBJECTS)
msp430_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_DEPENDENCIES = \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_msp430_TRUE@ %,msp430/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_msp430_TRUE@ %,msp430/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/msp430-sim.o \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/sim-resume.o
@SIM_ENABLE_ARCH_msp430_TRUE@am_msp430_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_msp430_TRUE@nodist_msp430_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/modules.$(OBJEXT)
msp430_libsim_a_OBJECTS = $(am_msp430_libsim_a_OBJECTS) \
$(nodist_msp430_libsim_a_OBJECTS)
or1k_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_or1k_TRUE@ %,or1k/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_or1k_TRUE@ %,or1k/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-accfp.o or1k/cgen-fpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-run.o or1k/cgen-scache.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-trace.o or1k/cgen-utils.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/arch.o or1k/cpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/decode.o or1k/mloop.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/model.o or1k/sem.o or1k/or1k.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sim-if.o or1k/traps.o
@SIM_ENABLE_ARCH_or1k_TRUE@am_or1k_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_or1k_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_or1k_TRUE@nodist_or1k_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/modules.$(OBJEXT)
or1k_libsim_a_OBJECTS = $(am_or1k_libsim_a_OBJECTS) \
$(nodist_or1k_libsim_a_OBJECTS)
ppc_libigen_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_DEPENDENCIES = igen/filter.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter_host.o igen/lf.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ igen/misc.o
@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libigen_a_OBJECTS = \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/table.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/lf-ppc.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/dumpf.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/filter-ppc.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-model.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-itable.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-icache.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-semantics.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-idecode.$(OBJEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-support.$(OBJEXT)
ppc_libigen_a_OBJECTS = $(am_ppc_libigen_a_OBJECTS)
ppc_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_DEPENDENCIES = ppc/debug.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/bits.o ppc/sim-endian.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/os_emul.o ppc/emul_generic.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_bugapi.o ppc/emul_chirp.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_netbsd.o ppc/emul_unix.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/registers.o ppc/vm.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/corefile.o ppc/model.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/spreg.o ppc/cpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/interrupts.o ppc/events.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cap.o ppc/device.o ppc/tree.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device_table.o ppc/itable.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/mon.o ppc/icache.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.o ppc/idecode.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.o ppc/sim-fpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim.o ppc/pk_disklabel.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_ppc_TRUE@ %,ppc/%,$(sim_ppc_hw_obj)) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/options.o ppc/gdb-sim.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim_calls.o
@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libsim_a_OBJECTS = $(am__objects_1)
ppc_libsim_a_OBJECTS = $(am_ppc_libsim_a_OBJECTS)
pru_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_pru_TRUE@ %,pru/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_pru_TRUE@ %,pru/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o pru/sim-resume.o
@SIM_ENABLE_ARCH_pru_TRUE@am_pru_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_pru_TRUE@nodist_pru_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/modules.$(OBJEXT)
pru_libsim_a_OBJECTS = $(am_pru_libsim_a_OBJECTS) \
$(nodist_pru_libsim_a_OBJECTS)
riscv_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_riscv_TRUE@ %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_riscv_TRUE@ %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o riscv/machs.o \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-main.o \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-resume.o
@SIM_ENABLE_ARCH_riscv_TRUE@am_riscv_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_riscv_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_riscv_TRUE@nodist_riscv_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.$(OBJEXT)
riscv_libsim_a_OBJECTS = $(am_riscv_libsim_a_OBJECTS) \
$(nodist_riscv_libsim_a_OBJECTS)
rl78_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_DEPENDENCIES = rl78/load.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/mem.o rl78/cpu.o rl78/rl78.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/gdb-if.o rl78/trace.o
@SIM_ENABLE_ARCH_rl78_TRUE@am_rl78_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_rl78_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_rl78_TRUE@nodist_rl78_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/modules.$(OBJEXT)
rl78_libsim_a_OBJECTS = $(am_rl78_libsim_a_OBJECTS) \
$(nodist_rl78_libsim_a_OBJECTS)
rx_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_DEPENDENCIES = rx/fpu.o rx/load.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/mem.o rx/misc.o rx/reg.o rx/rx.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/syscalls.o rx/trace.o rx/gdb-if.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/err.o
@SIM_ENABLE_ARCH_rx_TRUE@am_rx_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_rx_TRUE@nodist_rx_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/modules.$(OBJEXT)
rx_libsim_a_OBJECTS = $(am_rx_libsim_a_OBJECTS) \
$(nodist_rx_libsim_a_OBJECTS)
sh_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_DEPENDENCIES = sh/interp.o \
@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_sh_TRUE@ %,sh/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_sh_TRUE@ %,sh/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.o
@SIM_ENABLE_ARCH_sh_TRUE@am_sh_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_sh_TRUE@nodist_sh_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/modules.$(OBJEXT)
sh_libsim_a_OBJECTS = $(am_sh_libsim_a_OBJECTS) \
$(nodist_sh_libsim_a_OBJECTS)
v850_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_v850_TRUE@ %,v850/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_v850_TRUE@ %,v850/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/simops.o v850/interp.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.o v850/semantics.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.o v850/icache.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.o v850/irun.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.o v850/sim-resume.o
@SIM_ENABLE_ARCH_v850_TRUE@am_v850_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_v850_TRUE@ $(am__objects_1)
@SIM_ENABLE_ARCH_v850_TRUE@nodist_v850_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/modules.$(OBJEXT)
v850_libsim_a_OBJECTS = $(am_v850_libsim_a_OBJECTS) \
$(nodist_v850_libsim_a_OBJECTS)
am__EXEEXT_1 = $(IGEN) igen/filter$(EXEEXT) igen/gen$(EXEEXT) \
igen/ld-cache$(EXEEXT) igen/ld-decode$(EXEEXT) \
igen/ld-insn$(EXEEXT) igen/table$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_2 = cr16/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_3 = d10v/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_4 = m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_5 = m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_6 = $(PPC_IGEN) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache$(EXEEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode$(EXEEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_7 = $(am__EXEEXT_6)
@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_8 = sh/gencode$(EXEEXT)
am__EXEEXT_9 = testsuite/common/bits32m0$(EXEEXT) \
testsuite/common/bits32m31$(EXEEXT) \
testsuite/common/bits64m0$(EXEEXT) \
testsuite/common/bits64m63$(EXEEXT) \
testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_10 = cris/rvdummy$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_11 = aarch64/run$(EXEEXT)
@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_12 = arm/run$(EXEEXT)
@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_13 = avr/run$(EXEEXT)
@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_14 = bfin/run$(EXEEXT)
@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_15 = bpf/run$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_16 = cr16/run$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_17 = cris/run$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_18 = d10v/run$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_19 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis$(EXEEXT)
@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_20 = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/run$(EXEEXT)
@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_21 = frv/run$(EXEEXT)
@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_22 = ft32/run$(EXEEXT)
@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_23 = h8300/run$(EXEEXT)
@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_24 = iq2000/run$(EXEEXT)
@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_25 = lm32/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_26 = m32c/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_27 = m32r/run$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_28 = m68hc11/run$(EXEEXT)
@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_29 = mcore/run$(EXEEXT)
@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_30 = \
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sim_ppc_hw_src = @sim_ppc_hw_src@
sim_ppc_icache = @sim_ppc_icache@
sim_ppc_igen_smp = @sim_ppc_igen_smp@
sim_ppc_jump = @sim_ppc_jump@
sim_ppc_line_nr = @sim_ppc_line_nr@
sim_ppc_model = @sim_ppc_model@
sim_ppc_model_issue = @sim_ppc_model_issue@
sim_ppc_monitor = @sim_ppc_monitor@
sim_ppc_opcode = @sim_ppc_opcode@
sim_ppc_smp = @sim_ppc_smp@
sim_ppc_switch = @sim_ppc_switch@
sim_ppc_timebase = @sim_ppc_timebase@
sim_ppc_xor_endian = @sim_ppc_xor_endian@
srcdir = @srcdir@
sysconfdir = @sysconfdir@
target = @target@
target_alias = @target_alias@
target_cpu = @target_cpu@
target_os = @target_os@
target_vendor = @target_vendor@
top_build_prefix = @top_build_prefix@
top_builddir = @top_builddir@
top_srcdir = @top_srcdir@
AUTOMAKE_OPTIONS = dejagnu foreign no-dist subdir-objects
ACLOCAL_AMFLAGS = -Im4 -I.. -I../config
GNULIB_PARENT_DIR = ..
srccom = $(srcdir)/common
srcroot = $(srcdir)/..
pkginclude_HEADERS = $(am__append_1)
EXTRA_LIBRARIES = igen/libigen.a $(am__append_101)
noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \
$(am__append_7) $(am__append_9) $(am__append_11) \
$(am__append_13) $(am__append_19) $(am__append_25) \
$(am__append_31) $(am__append_35) $(am__append_37) \
$(am__append_42) $(am__append_44) $(am__append_46) \
$(am__append_51) $(am__append_56) $(am__append_60) \
$(am__append_65) $(am__append_69) $(am__append_71) \
$(am__append_76) $(am__append_84) $(am__append_88) \
$(am__append_90) $(am__append_92) $(am__append_97) \
$(am__append_103) $(am__append_105) $(am__append_107) \
$(am__append_109) $(am__append_111) $(am__append_116)
BUILT_SOURCES = $(am__append_15) $(am__append_22) $(am__append_27) \
$(am__append_39) $(am__append_48) $(am__append_53) \
$(am__append_62) $(am__append_78) $(am__append_86) \
$(am__append_94) $(am__append_99) $(am__append_113) \
$(am__append_118)
CLEANFILES = common/version.c common/version.c-stamp \
testsuite/common/bits-gen testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
testsuite/common/bits64m63.c $(am__append_17) $(am__append_23) \
$(am__append_29) $(am__append_40) $(am__append_49) \
$(am__append_54) $(am__append_63) $(am__append_95)
DISTCLEANFILES = $(am__append_83)
MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \
$(SIM_ENABLED_ARCHES:%=%/hw-config.h) \
$(SIM_ENABLED_ARCHES:%=%/stamp-hw) \
$(SIM_ENABLED_ARCHES:%=%/modules.c) \
$(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \
igen/libigen.a site-sim-config.exp testrun.log testrun.sum \
$(am__append_18) $(am__append_24) $(am__append_30) \
$(am__append_41) $(am__append_50) $(am__append_55) \
$(am__append_59) $(am__append_64) $(am__append_68) \
$(am__append_82) $(am__append_87) $(am__append_96) \
$(am__append_100) $(am__append_115) $(am__append_119)
CONFIG_STATUS_DEPENDENCIES = $(srcroot)/bfd/development.sh
AM_CFLAGS = \
$(WERROR_CFLAGS) \
$(WARN_CFLAGS) \
$(AM_CFLAGS_$(subst -,_,$(@D))) \
$(AM_CFLAGS_$(subst -,_,$(@D)_$(@F)))
AM_CPPFLAGS = $(INCGNU) -I$(srcroot) -I$(srcroot)/include -I../bfd \
-I.. -I$(@D) -I$(srcdir)/$(@D) $(SIM_HW_CFLAGS) $(SIM_INLINE) \
$(AM_CPPFLAGS_$(subst -,_,$(@D))) $(AM_CPPFLAGS_$(subst \
-,_,$(@D)_$(@F))) -I$(srcdir)/common -DSIM_TOPDIR_BUILD
AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \
$(SIM_INLINE) -I$(srcdir)/common
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(BUILD_WERROR_CFLAGS) $(BUILD_WARN_CFLAGS)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_INSTALL_DATA_LOCAL_DEPS =
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_33)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_34)
SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
SIM_COMPILE = \
$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \
$(am__mv) $(SIM_DEPBASE).Tpo $(SIM_DEPBASE).Po
AM_CPPFLAGS_common = -DSIM_COMMON_BUILD
common_libcommon_a_SOURCES = \
common/callback.c \
common/portability.c \
common/sim-load.c \
common/sim-signal.c \
common/syscall.c \
common/target-newlib-errno.c \
common/target-newlib-open.c \
common/target-newlib-signal.c \
common/target-newlib-syscall.c \
common/version.c
SIM_COMMON_HW_OBJS = \
hw-alloc.o \
hw-base.o \
hw-device.o \
hw-events.o \
hw-handles.o \
hw-instances.o \
hw-ports.o \
hw-properties.o \
hw-tree.o \
sim-hw.o
SIM_NEW_COMMON_OBJS = sim-arange.o sim-bits.o sim-close.o \
sim-command.o sim-config.o sim-core.o sim-cpu.o sim-endian.o \
sim-engine.o sim-events.o sim-fpu.o sim-hload.o sim-hrw.o \
sim-io.o sim-info.o sim-memopt.o sim-model.o sim-module.o \
sim-options.o sim-profile.o sim-reason.o sim-reg.o sim-stop.o \
sim-syscall.o sim-trace.o sim-utils.o sim-watch.o \
$(am__append_2)
SIM_HW_DEVICES = cfi core pal glue
am_arch_d = $(subst -,_,$(@D))
GEN_MODULES_C_SRCS = \
$(wildcard \
$(patsubst %,$(srcdir)/%,$($(am_arch_d)_libsim_a_SOURCES)) \
$(patsubst %.o,$(srcdir)/%.c,$($(am_arch_d)_libsim_a_OBJECTS) $($(am_arch_d)_libsim_a_LIBADD)) \
$(filter-out %.o,$(patsubst $(@D)/%.o,$(srcdir)/common/%.c,$($(am_arch_d)_libsim_a_LIBADD))))
LIBIBERTY_LIB = ../libiberty/libiberty.a
BFD_LIB = ../bfd/libbfd.la
OPCODES_LIB = ../opcodes/libopcodes.la
SIM_COMMON_LIBS = \
$(BFD_LIB) \
$(OPCODES_LIB) \
$(LIBIBERTY_LIB) \
$(LIBGNU) \
$(LIBGNU_EXTRA_LIBS)
GUILE = guile
CGEN = "$(GUILE) -l $(cgendir)/guile.scm -s"
CGENFLAGS = -v
CGEN_CPU_DIR = $(cgendir)/cpu
CPU_DIR = $(srcroot)/cpu
CGEN_ARCHFILE = $(CPU_DIR)/$(@D).cpu
CGEN_READ_SCM = $(cgendir)/sim.scm
CGEN_ARCH_SCM = $(cgendir)/sim-arch.scm
CGEN_CPU_SCM = $(cgendir)/sim-cpu.scm $(cgendir)/sim-model.scm
CGEN_DECODE_SCM = $(cgendir)/sim-decode.scm
CGEN_DESC_SCM = $(cgendir)/desc.scm $(cgendir)/desc-cpu.scm
CGEN_CPU_EXTR = /extr/
CGEN_CPU_READ = /read/
CGEN_CPU_WRITE = /write/
CGEN_CPU_SEM = /sem/
CGEN_CPU_SEMSW = /semsw/
CGEN_WRAPPER = $(srccom)/cgen.sh
CGEN_GEN_ARCH = \
$(SHELL) $(CGEN_WRAPPER) arch $(srcdir)/$(@D) \
$(CGEN) $(cgendir) "$(CGENFLAGS)" \
$(@D) "$$FLAGS" ignored "$$isa" $$mach ignored \
$(CGEN_ARCHFILE) ignored
CGEN_GEN_CPU = \
$(SHELL) $(CGEN_WRAPPER) cpu $(srcdir)/$(@D) \
$(CGEN) $(cgendir) "$(CGENFLAGS)" \
$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
$(CGEN_ARCHFILE) "$$EXTRAFILES"
CGEN_GEN_DEFS = \
$(SHELL) $(CGEN_WRAPPER) defs $(srcdir)/$(@D) \
$(CGEN) $(cgendir) "$(CGENFLAGS)" \
$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
$(CGEN_ARCHFILE) ignored
CGEN_GEN_DECODE = \
$(SHELL) $(CGEN_WRAPPER) decode $(srcdir)/$(@D) \
$(CGEN) $(cgendir) "$(CGENFLAGS)" \
$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
$(CGEN_ARCHFILE) "$$EXTRAFILES"
CGEN_GEN_CPU_DECODE = \
$(SHELL) $(CGEN_WRAPPER) cpu-decode $(srcdir)/$(@D) \
$(CGEN) $(cgendir) "$(CGENFLAGS)" \
$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
$(CGEN_ARCHFILE) "$$EXTRAFILES"
CGEN_GEN_CPU_DESC = \
$(SHELL) $(CGEN_WRAPPER) desc $(srcdir)/$(@D) \
$(CGEN) $(cgendir) "$(CGENFLAGS)" \
$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
$(CGEN_ARCHFILE) ignored $$opcfile
CGEN_GEN_MLOOP = \
$(SHELL) $(srccom)/lineno.sh \
$(srccom)/genmloop.sh \
$@.lineno.sh \
-shell $(SHELL) -awk $(AWK) -lineno $(srccom)/lineno.sh \
-infile $< -outfile-prefix $(@D)/
# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
IGEN = igen/igen$(EXEEXT)
IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP)
igen_libigen_a_SOURCES = \
igen/table.c \
igen/lf.c \
igen/misc.c \
igen/filter_host.c \
igen/ld-decode.c \
igen/ld-cache.c \
igen/filter.c \
igen/ld-insn.c \
igen/gen-model.c \
igen/gen-itable.c \
igen/gen-icache.c \
igen/gen-semantics.c \
igen/gen-idecode.c \
igen/gen-support.c \
igen/gen-engine.c \
igen/gen.c
igen_igen_SOURCES = igen/igen.c
igen_igen_LDADD = igen/libigen.a
igen_filter_SOURCES =
igen_filter_LDADD = igen/filter-main.o igen/libigen.a
igen_gen_SOURCES =
igen_gen_LDADD = igen/gen-main.o igen/libigen.a
igen_ld_cache_SOURCES =
igen_ld_cache_LDADD = igen/ld-cache-main.o igen/libigen.a
igen_ld_decode_SOURCES =
igen_ld_decode_LDADD = igen/ld-decode-main.o igen/libigen.a
igen_ld_insn_SOURCES =
igen_ld_insn_LDADD = igen/ld-insn-main.o igen/libigen.a
igen_table_SOURCES =
igen_table_LDADD = igen/table-main.o igen/libigen.a
igen_IGEN_TOOLS = \
$(IGEN) \
igen/filter \
igen/gen \
igen/ld-cache \
igen/ld-decode \
igen/ld-insn \
igen/table
EXTRA_DEJAGNU_SITE_CONFIG = site-sim-config.exp
# Custom verbose test variables that automake doesn't provide (yet?).
AM_V_RUNTEST = $(AM_V_RUNTEST_@AM_V@)
AM_V_RUNTEST_ = $(AM_V_RUNTEST_@AM_DEFAULT_V@)
AM_V_RUNTEST_0 = @echo " RUNTEST $(RUNTESTFLAGS) $*";
AM_V_RUNTEST_1 =
DO_RUNTEST = \
LC_ALL=C; export LC_ALL; \
EXPECT=${EXPECT} ; export EXPECT ; \
runtest=$(RUNTEST); \
$$runtest $(RUNTESTFLAGS)
testsuite_common_CPPFLAGS = \
-I$(srcdir)/common \
-I$(srcroot)/include \
-I../bfd
@SIM_ENABLE_ARCH_aarch64_TRUE@nodist_aarch64_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/modules.c
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(patsubst %,aarch64/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(patsubst %,aarch64/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/cpustate.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/interp.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/memory.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/sim-resume.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/simulator.o
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_SOURCES =
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_LDADD = \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/nrun.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_arm_TRUE@AM_CPPFLAGS_arm = -DMODET
@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.c
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_arm_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/wrapper.o \
@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armvirt.o arm/thumbemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armcopro.o arm/maverick.o arm/iwmmxt.o
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES =
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a \
@SIM_ENABLE_ARCH_arm_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm
@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README
@SIM_ENABLE_ARCH_avr_TRUE@nodist_avr_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/modules.c
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_avr_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/interp.o \
@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/sim-resume.o
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_SOURCES =
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_LDADD = \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/nrun.o \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/libsim.a \
@SIM_ENABLE_ARCH_avr_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_bfin_TRUE@AM_CPPFLAGS_bfin = $(SDL_CFLAGS)
@SIM_ENABLE_ARCH_bfin_TRUE@nodist_bfin_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/modules.c
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bfin_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/bfin-sim.o \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/devices.o \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/gui.o \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/interp.o \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/machs.o \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/sim-resume.o
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_SOURCES =
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_LDADD = \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/nrun.o \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/libsim.a \
@SIM_ENABLE_ARCH_bfin_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_SIM_EXTRA_HW_DEVICES = \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_cec \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ctimer \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_dma \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_dmac \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_amc \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_ddrc \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_sdc \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_emac \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_eppi \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_evt \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gpio \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gpio2 \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gptimer \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_jtag \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_mmu \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_nfc \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_otp \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pfmon \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pint \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pll \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ppi \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_rtc \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_sic \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_spi \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_trace \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_twi \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_uart \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_uart2 \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wdog \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wp \
@SIM_ENABLE_ARCH_bfin_TRUE@ eth_phy
@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.c
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-sim.o \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES =
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/nrun.o \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/libsim.a \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/modules.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cr16_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/interp.o \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/sim-resume.o \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/simops.o \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.o
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_SOURCES =
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_LDADD = \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/nrun.o \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/libsim.a \
@SIM_ENABLE_ARCH_cr16_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE) \
@SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_CFLAG_WNO_SHADOW_LOCAL)
@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv32f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE)
@SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/modules.c
@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cris_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@ \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-run.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-scache.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-trace.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-utils.o \
@SIM_ENABLE_ARCH_cris_TRUE@ \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/arch.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv10.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev10.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv10.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv32f.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev32.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.o \
@SIM_ENABLE_ARCH_cris_TRUE@ \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/sim-if.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/traps.o
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_SOURCES =
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_LDADD = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/nrun.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/libsim.a \
@SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_cris_TRUE@cris_SIM_EXTRA_HW_DEVICES = rv cris cris_900000xx
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_SOURCES = cris/rvdummy.c
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_LDADD = $(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_cris_TRUE@cris_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv10f.c \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v10f \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.c \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v32f
@SIM_ENABLE_ARCH_d10v_TRUE@nodist_d10v_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/modules.c
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_d10v_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/interp.o \
@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/endian.o \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/sim-resume.o \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/simops.o \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES =
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD = \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/nrun.o \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/libsim.a \
@SIM_ENABLE_ARCH_d10v_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.c
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD = d10v/d10v-opc.o
@SIM_ENABLE_ARCH_erc32_TRUE@READLINE_SRC = $(srcroot)/readline/readline
@SIM_ENABLE_ARCH_erc32_TRUE@AM_CPPFLAGS_erc32 = $(READLINE_CFLAGS) \
@SIM_ENABLE_ARCH_erc32_TRUE@ -DFAST_UART
@SIM_ENABLE_ARCH_erc32_TRUE@nodist_erc32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/modules.c
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_erc32_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/erc32.o \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/exec.o \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/float.o \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/func.o \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/help.o \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/interf.o
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES =
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD = \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis.o \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/libsim.a \
@SIM_ENABLE_ARCH_erc32_TRUE@ $(SIM_COMMON_LIBS) $(READLINE_LIB) $(TERMCAP_LIB)
@SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32
@SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis
@SIM_ENABLE_ARCH_examples_TRUE@nodist_example_synacor_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/modules.c
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_examples_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/interp.o \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-main.o \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-resume.o
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES =
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/nrun.o \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/libsim.a \
@SIM_ENABLE_ARCH_examples_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_frv_TRUE@AM_CPPFLAGS_frv = $(SIM_FRV_TRAPDUMP_FLAGS)
@SIM_ENABLE_ARCH_frv_TRUE@nodist_frv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/modules.c
@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_frv_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_frv_TRUE@ \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-accfp.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-fpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-run.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-scache.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-trace.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-utils.o \
@SIM_ENABLE_ARCH_frv_TRUE@ \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/arch.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-par.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/decode.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/frv.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/model.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/sem.o \
@SIM_ENABLE_ARCH_frv_TRUE@ \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/cache.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/interrupts.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/memory.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/options.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/pipeline.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr400.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr450.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr500.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr550.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/registers.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/reset.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/sim-if.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/traps.o
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_SOURCES =
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_LDADD = \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/nrun.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/libsim.a \
@SIM_ENABLE_ARCH_frv_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_frv_TRUE@frvdocdir = $(docdir)/frv
@SIM_ENABLE_ARCH_frv_TRUE@frvdoc_DATA = frv/README
@SIM_ENABLE_ARCH_frv_TRUE@frv_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.c \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/stamp-mloop
@SIM_ENABLE_ARCH_ft32_TRUE@nodist_ft32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/modules.c
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_ft32_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/interp.o \
@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/sim-resume.o
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES =
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \
@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/nrun.o \
@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/libsim.a \
@SIM_ENABLE_ARCH_ft32_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_h8300_TRUE@nodist_h8300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/modules.c
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_h8300_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/compile.o \
@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/sim-resume.o
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_SOURCES =
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_LDADD = \
@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/nrun.o \
@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/libsim.a \
@SIM_ENABLE_ARCH_h8300_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_iq2000_TRUE@nodist_iq2000_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/modules.c
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@ \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-run.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-scache.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-trace.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-utils.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/arch.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cpu.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/decode.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/iq2000.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sem.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/model.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sim-if.o
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES =
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/nrun.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/libsim.a \
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.c \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/stamp-mloop
@SIM_ENABLE_ARCH_lm32_TRUE@nodist_lm32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/modules.c
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_lm32_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@ \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-run.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-scache.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-trace.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-utils.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/arch.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cpu.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/decode.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sem.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/model.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/lm32.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sim-if.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/traps.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/user.o
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES =
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/nrun.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/libsim.a \
@SIM_ENABLE_ARCH_lm32_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_SIM_EXTRA_HW_DEVICES = lm32cpu lm32timer lm32uart
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.c \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/stamp-mloop
@SIM_ENABLE_ARCH_m32c_TRUE@AM_CPPFLAGS_m32c = -DTIMER_A
@SIM_ENABLE_ARCH_m32c_TRUE@nodist_m32c_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/modules.c
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/gdb-if.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/int.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/load.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/mem.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/misc.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/reg.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/srcdest.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/syscalls.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES =
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/main.o \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/libsim.a \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/opc2c$(EXEEXT) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_opc2c_SOURCES = m32c/opc2c.c
# opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.c
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@ \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-run.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-utils.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sem.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpux.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modelx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/traps.o
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES =
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/nrun.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/libsim.a \
@SIM_ENABLE_ARCH_m32r_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_SIM_EXTRA_HW_DEVICES = m32r_cache m32r_uart
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.c \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.c \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-x \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.c \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-2
@SIM_ENABLE_ARCH_m68hc11_TRUE@AM_CPPFLAGS_m68hc11 = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_BITSIZE=32 \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_CELL_BITSIZE=32 \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_ADDRESS_BITSIZE=32 \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_MSB=31
@SIM_ENABLE_ARCH_m68hc11_TRUE@nodist_m68hc11_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11_sim.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES =
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/nrun.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/libsim.a \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_SIM_EXTRA_HW_DEVICES = m68hc11 m68hc11sio m68hc11eepr m68hc11tim m68hc11spi nvram
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.c \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
@SIM_ENABLE_ARCH_mcore_TRUE@nodist_mcore_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.c
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/sim-resume.o
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES =
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/nrun.o \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/libsim.a \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_microblaze_TRUE@nodist_microblaze_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.c
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES =
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/nrun.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/libsim.a \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_mips_TRUE@AM_CPPFLAGS_mips = \
@SIM_ENABLE_ARCH_mips_TRUE@ @SIM_MIPS_SUBTARGET@ \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_GEN_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/cp1.o \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.o \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-main.o \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-resume.o
@SIM_ENABLE_ARCH_mips_TRUE@EXTRA_mips_libsim_a_DEPENDENCIES = $(SIM_MIPS_MULTI_OBJ)
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES =
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/nrun.o \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/libsim.a \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_mips_TRUE@mips_SIM_EXTRA_HW_DEVICES = tx3904cpu tx3904irc tx3904tmr tx3904sio
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_IGEN_ITABLE = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/itable.c
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_SINGLE = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/model.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/model.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/support.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/support.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/engine.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/engine.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/irun.c
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M16 = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_support.c \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M32 = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_support.c
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp2.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16e.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/micromipsdsp.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/micromips.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3264r2.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3264r6.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3d.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/sb1.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/tx.igen \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/vr.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_DC = $(srcdir)/mips/mips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS32_DC = $(srcdir)/mips/micromips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS16_DC = $(srcdir)/mips/micromips16.dc
@SIM_ENABLE_ARCH_mn10300_TRUE@AM_CPPFLAGS_mn10300 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ -DPOLL_QUIT_INTERVAL=0x20 \
@SIM_ENABLE_ARCH_mn10300_TRUE@ -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31
@SIM_ENABLE_ARCH_mn10300_TRUE@nodist_mn10300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/modules.c
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/interp.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/op_utils.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/sim-resume.o
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES =
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/libsim.a \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_SIM_EXTRA_HW_DEVICES = mn103cpu mn103int mn103tim mn103ser mn103iop
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/model.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/model.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.c
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(mn10300_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/stamp-igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN = $(srcdir)/mn10300/mn10300.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN_INC = mn10300/am33.igen mn10300/am33-2.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_DC = $(srcdir)/mn10300/mn10300.dc
@SIM_ENABLE_ARCH_moxie_TRUE@AM_CPPFLAGS_moxie = -DDTB="\"$(dtbdir)/moxie-gdb.dtb\""
@SIM_ENABLE_ARCH_moxie_TRUE@nodist_moxie_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/modules.c
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_moxie_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/interp.o \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/sim-resume.o
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_SOURCES =
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_LDADD = \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/nrun.o \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/libsim.a \
@SIM_ENABLE_ARCH_moxie_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_moxie_TRUE@dtbdir = $(datadir)/gdb/dtb
@SIM_ENABLE_ARCH_moxie_TRUE@dtb_DATA = moxie/moxie-gdb.dtb
@SIM_ENABLE_ARCH_msp430_TRUE@nodist_msp430_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/modules.c
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/msp430-sim.o \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/sim-resume.o
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_SOURCES =
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_LDADD = \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/nrun.o \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/libsim.a \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_or1k_TRUE@AM_CPPFLAGS_or1k = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31
@SIM_ENABLE_ARCH_or1k_TRUE@nodist_or1k_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/modules.c
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_or1k_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_or1k_TRUE@ \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-accfp.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-fpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-run.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-scache.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-trace.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-utils.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/arch.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cpu.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/decode.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/model.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sem.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/or1k.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sim-if.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/traps.o
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_SOURCES =
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_LDADD = \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/nrun.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/libsim.a \
@SIM_ENABLE_ARCH_or1k_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1kdocdir = $(docdir)/or1k
@SIM_ENABLE_ARCH_or1k_TRUE@or1kdoc_DATA = or1k/README
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.c \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/stamp-mloop
@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc = \
@SIM_ENABLE_ARCH_ppc_TRUE@ -DHAVE_COMMON_FPU \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_smp) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_xor_endian) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_bitsize) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_timebase) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_float) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_monitor) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_model) $(sim_ppc_default_model) $(sim_ppc_model_issue) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_switch)
@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc_options.o = '-DOPCODE_RULES="$(IGEN_OPCODE_RULES)"' '-DIGEN_FLAGS="$(ppc_IGEN_FLAGS)"'
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/debug.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/bits.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-endian.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/os_emul.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_generic.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_bugapi.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_chirp.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_netbsd.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_unix.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/registers.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/vm.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/corefile.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/spreg.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/interrupts.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/events.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cap.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/tree.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device_table.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/mon.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-fpu.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/pk_disklabel.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(patsubst %,ppc/%,$(sim_ppc_hw_obj)) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/options.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gdb-sim.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim_calls.o
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES = \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/main.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_LDADD = \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/libsim.a \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_SOURCES = \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/table.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/lf-ppc.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/dumpf.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/filter-ppc.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-model.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-itable.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-icache.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-semantics.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-idecode.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-support.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_LIBADD = \
@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter_host.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ igen/lf.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ igen/misc.o
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_SOURCES = ppc/igen.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_LDADD = ppc/libigen.a
# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN = ppc/igen$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(PPC_IGEN) $(ppc_IGEN_FLAGS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_FLAGS = \
@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_decode_mechanism@ \
@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_dup@ \
@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_jump@ \
@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_filter@ \
@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_icache@ \
@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_igen_smp@ \
@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_line_nr@
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.c \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-igen ppc/hw.c ppc/hw.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-hw ppc/stamp-pk
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_OPCODE_RULES = ppc/@sim_ppc_opcode@
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_SOURCES =
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_LDADD = ppc/ld-cache-main.o ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_SOURCES =
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_LDADD = ppc/ld-decode-main.o ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_SOURCES =
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_LDADD = ppc/ld-insn-main.o ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_TOOLS = \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(PPC_IGEN) \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn
@SIM_ENABLE_ARCH_ppc_TRUE@IGEN_OPCODE_RULES = @sim_ppc_opcode@
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_HW_SRC = $(sim_ppc_hw_src:%=ppc/%)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_PACKAGE_SRC = ppc/pk_disklabel.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir = $(docdir)/ppc
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA = ppc/BUGS ppc/INSTALL ppc/README ppc/RUN
@SIM_ENABLE_ARCH_pru_TRUE@nodist_pru_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/modules.c
@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_pru_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/sim-resume.o
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_SOURCES =
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_LDADD = \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/nrun.o \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/libsim.a \
@SIM_ENABLE_ARCH_pru_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_riscv_TRUE@AM_CPPFLAGS_riscv = -DWITH_TARGET_WORD_BITSIZE=$(SIM_RISCV_BITSIZE)
@SIM_ENABLE_ARCH_riscv_TRUE@nodist_riscv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.c
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_riscv_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/machs.o \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-main.o \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-resume.o
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_SOURCES =
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_LDADD = \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/nrun.o \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/libsim.a \
@SIM_ENABLE_ARCH_riscv_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_rl78_TRUE@nodist_rl78_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/modules.c
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rl78_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/load.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/mem.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/cpu.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/rl78.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/gdb-if.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/trace.o
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_SOURCES =
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_LDADD = \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/main.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/libsim.a \
@SIM_ENABLE_ARCH_rl78_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_rx_TRUE@AM_CPPFLAGS_rx = $(SIM_RX_CYCLE_ACCURATE_FLAGS)
@SIM_ENABLE_ARCH_rx_TRUE@nodist_rx_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/modules.c
@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_rx_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/fpu.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/load.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/mem.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/misc.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/reg.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/rx.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/syscalls.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/trace.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/gdb-if.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/err.o
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_SOURCES =
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_LDADD = \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/main.o \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/libsim.a \
@SIM_ENABLE_ARCH_rx_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_rx_TRUE@rxdocdir = $(docdir)/rx
@SIM_ENABLE_ARCH_rx_TRUE@rxdoc_DATA = rx/README.txt
@SIM_ENABLE_ARCH_sh_TRUE@nodist_sh_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/modules.c
@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_sh_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/interp.o \
@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.o
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_SOURCES =
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_LDADD = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/nrun.o \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/libsim.a \
@SIM_ENABLE_ARCH_sh_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_sh_TRUE@sh_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.c
@SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c
@SIM_ENABLE_ARCH_v850_TRUE@AM_CPPFLAGS_v850 = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31
@SIM_ENABLE_ARCH_v850_TRUE@nodist_v850_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/modules.c
@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_v850_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/simops.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/interp.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/irun.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/sim-resume.o
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_SOURCES =
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_LDADD = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/nrun.o \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/libsim.a \
@SIM_ENABLE_ARCH_v850_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.c \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.c \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.c \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/model.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/model.c \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.c \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.c \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.c \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/irun.c
@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_v850_TRUE@ $(v850_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/stamp-igen
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_INSN = $(srcdir)/v850/v850.igen
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_DC = $(srcdir)/v850/v850.dc
all: $(BUILT_SOURCES) config.h
$(MAKE) $(AM_MAKEFLAGS) all-am
.SUFFIXES:
.SUFFIXES: .c .lo .log .o .obj .test .test$(EXEEXT) .trs
am--refresh: Makefile
@:
$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__configure_deps)
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
echo ' cd $(srcdir) && $(AUTOMAKE) --foreign'; \
$(am__cd) $(srcdir) && $(AUTOMAKE) --foreign \
&& exit 0; \
exit 1;; \
esac; \
done; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \
$(am__cd) $(top_srcdir) && \
$(AUTOMAKE) --foreign Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \
*config.status*) \
echo ' $(SHELL) ./config.status'; \
$(SHELL) ./config.status;; \
*) \
echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \
cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \
esac;
$(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__empty):
$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
$(SHELL) ./config.status --recheck
$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
$(am__cd) $(srcdir) && $(AUTOCONF)
$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
$(am__cd) $(srcdir) && $(ACLOCAL) $(ACLOCAL_AMFLAGS)
$(am__aclocal_m4_deps):
config.h: stamp-h1
@test -f $@ || rm -f stamp-h1
@test -f $@ || $(MAKE) $(AM_MAKEFLAGS) stamp-h1
stamp-h1: $(srcdir)/config.h.in $(top_builddir)/config.status
@rm -f stamp-h1
cd $(top_builddir) && $(SHELL) ./config.status config.h
$(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
($(am__cd) $(top_srcdir) && $(AUTOHEADER))
rm -f stamp-h1
touch $@
distclean-hdr:
-rm -f config.h stamp-h1
aarch64/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
arm/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
avr/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
bfin/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
bpf/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
cr16/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
cris/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
d10v/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
frv/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
ft32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
h8300/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
iq2000/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
lm32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
m32c/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
m32r/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
m68hc11/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
mcore/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
microblaze/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
mips/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
mn10300/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
moxie/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
msp430/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
or1k/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
ppc/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
pru/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
riscv/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
rl78/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
rx/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
sh/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
erc32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
v850/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
example-synacor/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
.gdbinit: $(top_builddir)/config.status $(srcdir)/gdbinit.in
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ppc/main.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)/$(am__dirstamp)
ppc/run$(EXEEXT): $(ppc_run_OBJECTS) $(ppc_run_DEPENDENCIES) $(EXTRA_ppc_run_DEPENDENCIES) ppc/$(am__dirstamp)
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pru/run$(EXEEXT): $(pru_run_OBJECTS) $(pru_run_DEPENDENCIES) $(EXTRA_pru_run_DEPENDENCIES) pru/$(am__dirstamp)
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