| // -*- C -*- |
| // |
| // <insn> ::= |
| // <insn-word> { "+" <insn-word> } |
| // ":" <format-name> |
| // ":" <filter-flags> |
| // ":" <options> |
| // ":" <name> |
| // <nl> |
| // { <insn-model> } |
| // { <insn-mnemonic> } |
| // <code-block> |
| // |
| |
| |
| // IGEN config - mips16 |
| // :option:16::insn-bit-size:16 |
| // :option:16::hi-bit-nr:15 |
| :option:16::insn-specifying-widths:true |
| :option:16::gen-delayed-branch:false |
| |
| // IGEN config - mips32/64.. |
| // :option:32::insn-bit-size:32 |
| // :option:32::hi-bit-nr:31 |
| :option:32::insn-specifying-widths:true |
| :option:32::gen-delayed-branch:false |
| |
| |
| // Generate separate simulators for each target |
| // :option:::multi-sim:true |
| |
| |
| // Models known by this simulator are defined below. |
| // |
| // When placing models in the instruction descriptions, please place |
| // them one per line, in the order given here. |
| |
| // MIPS ISAs: |
| // |
| // Instructions and related functions for these models are included in |
| // this file. |
| :model:::mipsI:mips3000: |
| :model:::mipsII:mips6000: |
| :model:::mipsIII:mips4000: |
| :model:::mipsIV:mips8000: |
| :model:::mipsV:mipsisaV: |
| :model:::mips32:mipsisa32: |
| :model:::mips32r2:mipsisa32r2: |
| :model:::mips32r6:mipsisa32r6: |
| :model:::mips64:mipsisa64: |
| :model:::mips64r2:mipsisa64r2: |
| :model:::mips64r6:mipsisa64r6: |
| |
| // Vendor ISAs: |
| // |
| // Standard MIPS ISA instructions used for these models are listed here, |
| // as are functions needed by those standard instructions. Instructions |
| // which are model-dependent and which are not in the standard MIPS ISAs |
| // (or which pre-date or use different encodings than the standard |
| // instructions) are (for the most part) in separate .igen files. |
| :model:::vr4100:mips4100: // vr.igen |
| :model:::vr4120:mips4120: |
| :model:::vr5000:mips5000: |
| :model:::vr5400:mips5400: |
| :model:::vr5500:mips5500: |
| :model:::r3900:mips3900: // tx.igen |
| |
| // MIPS Application Specific Extensions (ASEs) |
| // |
| // Instructions for the ASEs are in separate .igen files. |
| // ASEs add instructions on to a base ISA. |
| :model:::mips16:mips16: // m16.igen (and m16.dc) |
| :model:::mips16e:mips16e: // m16e.igen |
| :model:::mips3d:mips3d: // mips3d.igen |
| :model:::mdmx:mdmx: // mdmx.igen |
| :model:::dsp:dsp: // dsp.igen |
| :model:::dsp2:dsp2: // dsp2.igen |
| :model:::smartmips:smartmips: // smartmips.igen |
| :model:::micromips32:micromips64: // micromips.igen |
| :model:::micromips64:micromips64: // micromips.igen |
| :model:::micromipsdsp:micromipsdsp: // micromipsdsp.igen |
| |
| // Vendor Extensions |
| // |
| // Instructions specific to these extensions are in separate .igen files. |
| // Extensions add instructions on to a base ISA. |
| :model:::sb1:sb1: // sb1.igen |
| |
| |
| // Pseudo instructions known by IGEN |
| :internal::::illegal: |
| { |
| SignalException (ReservedInstruction, 0); |
| } |
| |
| |
| // Pseudo instructions known by interp.c |
| // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK |
| 000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD |
| "rsvd <OP>" |
| { |
| SignalException (ReservedInstruction, instruction_0); |
| } |
| |
| |
| |
| // Helpers: |
| // |
| // Check if given instruction is CTI, if so signal |
| // |
| :function:::void:signal_if_cti:instruction_word instr |
| { |
| uint32_t maj = (instr & 0xfc000000) >> 26; |
| uint32_t special = instr & 0x3f; |
| if ((maj & 0x3e) == 0x06 /* Branch/Jump */ |
| || ((maj & 0x38) == 0 && !((maj & 0x6) == 0)) |
| || maj == 0x18 |
| || (maj & 0x37) == 0x32 |
| || (maj & 0x37) == 0x36 |
| || ((maj == 0) && (special == 0x9)) |
| /* DERET/ERET/WAIT */ |
| || ((maj == 0x10) && (instr & 0x02000000) |
| && (special == 0x1f || special == 0x18 || special == 0x20))) |
| { |
| SignalException (ReservedInstruction, instr); |
| } |
| } |
| |
| // |
| // Simulate a 32 bit delayslot instruction |
| // |
| |
| :function:::address_word:delayslot32:address_word target |
| { |
| instruction_word delay_insn; |
| sim_events_slip (SD, 1); |
| DSPC = CIA; |
| CIA = CIA + 4; /* NOTE not mips16 */ |
| STATE |= simDELAYSLOT; |
| delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ |
| signal_if_cti (SD_, delay_insn); |
| ENGINE_ISSUE_PREFIX_HOOK(); |
| idecode_issue (CPU_, delay_insn, (CIA)); |
| STATE &= ~simDELAYSLOT; |
| return target; |
| } |
| |
| // |
| // Simulate a 32 bit forbidden slot instruction |
| // |
| |
| :function:::address_word:forbiddenslot32: |
| *mips32r6: |
| *mips64r6: |
| { |
| instruction_word delay_insn; |
| sim_events_slip (SD, 1); |
| DSPC = CIA; |
| CIA = CIA + 4; |
| STATE |= simFORBIDDENSLOT; |
| delay_insn = IMEM32 (CIA); |
| signal_if_cti (SD_, delay_insn); |
| ENGINE_ISSUE_PREFIX_HOOK (); |
| idecode_issue (CPU_, delay_insn, (CIA)); |
| STATE &= ~simFORBIDDENSLOT; |
| return CIA + 4; |
| } |
| |
| :function:::address_word:nullify_next_insn32: |
| { |
| sim_events_slip (SD, 1); |
| dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); |
| return CIA + 8; |
| } |
| |
| |
| // Helper: |
| // |
| // Calculate an effective address given a base and an offset. |
| // |
| |
| :function:::address_word:loadstore_ea:address_word base, address_word offset |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| *micromips32: |
| { |
| return base + offset; |
| } |
| |
| :function:::address_word:loadstore_ea:address_word base, address_word offset |
| *mips64: |
| *mips64r2: |
| *micromips64: |
| *mips64r6: |
| { |
| #if 0 /* XXX FIXME: enable this only after some additional testing. */ |
| /* If in user mode and UX is not set, use 32-bit compatibility effective |
| address computations as defined in the MIPS64 Architecture for |
| Programmers Volume III, Revision 0.95, section 4.9. */ |
| if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) |
| == (ksu_user << status_KSU_shift)) |
| return (address_word)((int32_t)base + (int32_t)offset); |
| #endif |
| return base + offset; |
| } |
| |
| |
| // Helper: |
| // |
| // Check that a 32-bit register value is properly sign-extended. |
| // (See NotWordValue in ISA spec.) |
| // |
| |
| :function:::int:not_word_value:unsigned_word value |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *micromips32: |
| *micromips64: |
| *mips64r6: |
| { |
| #if WITH_TARGET_WORD_BITSIZE == 64 |
| return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
| #else |
| return 0; |
| #endif |
| } |
| |
| // Helper: |
| // |
| // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent |
| // theoretically portable code which invokes non-portable behaviour from |
| // running with no indication of the portability issue. |
| // (See definition of UNPREDICTABLE in ISA spec.) |
| // |
| |
| :function:::void:unpredictable: |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| } |
| |
| :function:::void:unpredictable: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *micromips32: |
| *micromips64: |
| *mips64r6: |
| { |
| unpredictable_action (CPU, CIA); |
| } |
| |
| |
| // Helpers: |
| // |
| // Check that an access to a HI/LO register meets timing requirements |
| // |
| // In all MIPS ISAs, |
| // |
| // OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO}) |
| // makes subsequent MF{HI or LO} UNPREDICTABLE. (1) |
| // |
| // The following restrictions exist for MIPS I - MIPS III: |
| // |
| // MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions |
| // in between makes MF UNPREDICTABLE. (2) |
| // |
| // MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions |
| // in between makes MF UNPREDICTABLE. (3) |
| // |
| // On the r3900, restriction (2) is not present, and restriction (3) is not |
| // present for multiplication. |
| // |
| // Unfortunately, there seems to be some confusion about whether the last |
| // two restrictions should apply to "MIPS IV" as well. One edition of |
| // the MIPS IV ISA says they do, but references in later ISA documents |
| // suggest they don't. |
| // |
| // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have |
| // these restrictions, while others, like the VR5500, don't. To accomodate |
| // such differences, the MIPS IV and MIPS V version of these helper functions |
| // use auxillary routines to determine whether the restriction applies. |
| |
| // check_mf_cycles: |
| // |
| // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo |
| // to check for restrictions (2) and (3) above. |
| // |
| :function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new |
| { |
| if (history->mf.timestamp + 3 > time) |
| { |
| sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", |
| itable[MY_INDEX].name, |
| new, (long) CIA, |
| (long) history->mf.cia); |
| return 0; |
| } |
| return 1; |
| } |
| |
| |
| // check_mt_hilo: |
| // |
| // Check for restriction (2) above (for ISAs/processors that have it), |
| // and record timestamps for restriction (1) above. |
| // |
| :function:::int:check_mt_hilo:hilo_history *history |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *vr4100: |
| *vr5000: |
| { |
| int64_t time = sim_events_time (SD); |
| int ok = check_mf_cycles (SD_, history, time, "MT"); |
| history->mt.timestamp = time; |
| history->mt.cia = CIA; |
| return ok; |
| } |
| |
| :function:::int:check_mt_hilo:hilo_history *history |
| *mipsIV: |
| *mipsV: |
| { |
| int64_t time = sim_events_time (SD); |
| int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD) |
| || check_mf_cycles (SD_, history, time, "MT")); |
| history->mt.timestamp = time; |
| history->mt.cia = CIA; |
| return ok; |
| } |
| |
| :function:::int:check_mt_hilo:hilo_history *history |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *r3900: |
| *micromips32: |
| *micromips64: |
| { |
| int64_t time = sim_events_time (SD); |
| history->mt.timestamp = time; |
| history->mt.cia = CIA; |
| return 1; |
| } |
| |
| |
| // check_mf_hilo: |
| // |
| // Check for restriction (1) above, and record timestamps for |
| // restriction (2) and (3) above. |
| // |
| :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| *micromips32: |
| *micromips64: |
| { |
| int64_t time = sim_events_time (SD); |
| int ok = 1; |
| if (peer != NULL |
| && peer->mt.timestamp > history->op.timestamp |
| && history->mt.timestamp < history->op.timestamp |
| && ! (history->mf.timestamp > history->op.timestamp |
| && history->mf.timestamp < peer->mt.timestamp) |
| && ! (peer->mf.timestamp > history->op.timestamp |
| && peer->mf.timestamp < peer->mt.timestamp)) |
| { |
| /* The peer has been written to since the last OP yet we have |
| not */ |
| sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", |
| itable[MY_INDEX].name, |
| (long) CIA, |
| (long) history->op.cia, |
| (long) peer->mt.cia); |
| ok = 0; |
| } |
| history->mf.timestamp = time; |
| history->mf.cia = CIA; |
| return ok; |
| } |
| |
| |
| |
| // check_mult_hilo: |
| // |
| // Check for restriction (3) above (for ISAs/processors that have it) |
| // for MULT ops, and record timestamps for restriction (1) above. |
| // |
| :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *vr4100: |
| *vr5000: |
| { |
| int64_t time = sim_events_time (SD); |
| int ok = (check_mf_cycles (SD_, hi, time, "OP") |
| && check_mf_cycles (SD_, lo, time, "OP")); |
| hi->op.timestamp = time; |
| lo->op.timestamp = time; |
| hi->op.cia = CIA; |
| lo->op.cia = CIA; |
| return ok; |
| } |
| |
| :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo |
| *mipsIV: |
| *mipsV: |
| { |
| int64_t time = sim_events_time (SD); |
| int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) |
| || (check_mf_cycles (SD_, hi, time, "OP") |
| && check_mf_cycles (SD_, lo, time, "OP"))); |
| hi->op.timestamp = time; |
| lo->op.timestamp = time; |
| hi->op.cia = CIA; |
| lo->op.cia = CIA; |
| return ok; |
| } |
| |
| :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *r3900: |
| *micromips32: |
| *micromips64: |
| { |
| /* FIXME: could record the fact that a stall occured if we want */ |
| int64_t time = sim_events_time (SD); |
| hi->op.timestamp = time; |
| lo->op.timestamp = time; |
| hi->op.cia = CIA; |
| lo->op.cia = CIA; |
| return 1; |
| } |
| |
| |
| // check_div_hilo: |
| // |
| // Check for restriction (3) above (for ISAs/processors that have it) |
| // for DIV ops, and record timestamps for restriction (1) above. |
| // |
| :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| int64_t time = sim_events_time (SD); |
| int ok = (check_mf_cycles (SD_, hi, time, "OP") |
| && check_mf_cycles (SD_, lo, time, "OP")); |
| hi->op.timestamp = time; |
| lo->op.timestamp = time; |
| hi->op.cia = CIA; |
| lo->op.cia = CIA; |
| return ok; |
| } |
| |
| :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo |
| *mipsIV: |
| *mipsV: |
| { |
| int64_t time = sim_events_time (SD); |
| int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) |
| || (check_mf_cycles (SD_, hi, time, "OP") |
| && check_mf_cycles (SD_, lo, time, "OP"))); |
| hi->op.timestamp = time; |
| lo->op.timestamp = time; |
| hi->op.cia = CIA; |
| lo->op.cia = CIA; |
| return ok; |
| } |
| |
| :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *micromips32: |
| *micromips64: |
| *mips64r6: |
| { |
| int64_t time = sim_events_time (SD); |
| hi->op.timestamp = time; |
| lo->op.timestamp = time; |
| hi->op.cia = CIA; |
| lo->op.cia = CIA; |
| return 1; |
| } |
| |
| |
| // Helper: |
| // |
| // Check that the 64-bit instruction can currently be used, and signal |
| // a ReservedInstruction exception if not. |
| // |
| |
| :function:::void:check_u64:instruction_word insn |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *vr4100: |
| *vr5000: |
| *vr5400: |
| *vr5500: |
| *r3900: |
| { |
| // The check should be similar to mips64 for any with PX/UX bit equivalents. |
| } |
| |
| :function:::void:check_u64:instruction_word insn |
| *mips16e: |
| *mips64: |
| *mips64r2: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *micromips64: |
| *micromips32: |
| *mips64r6: |
| { |
| #if 0 /* XXX FIXME: enable this only after some additional testing. */ |
| if (UserMode && (SR & (status_UX|status_PX)) == 0) |
| SignalException (ReservedInstruction, insn); |
| #endif |
| } |
| |
| |
| |
| // |
| // MIPS Architecture: |
| // |
| // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) |
| // |
| |
| |
| :function:::void:do_add:int rs, int rt, int rd |
| { |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| ALU32_BEGIN (GPR[rs]); |
| ALU32_ADD (GPR[rt]); |
| ALU32_END (GPR[rd]); /* This checks for overflow. */ |
| } |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_addi:int rs, int rt, uint16_t immediate |
| { |
| if (NotWordValue (GPR[rs])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| { |
| ALU32_BEGIN (GPR[rs]); |
| ALU32_ADD (EXTEND16 (immediate)); |
| ALU32_END (GPR[rt]); /* This checks for overflow. */ |
| } |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| :function:::void:do_andi:int rs, int rt, unsigned int immediate |
| { |
| TRACE_ALU_INPUT2 (GPR[rs], immediate); |
| GPR[rt] = GPR[rs] & immediate; |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| :function:::void:do_dadd:int rd, int rs, int rt |
| { |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| ALU64_BEGIN (GPR[rs]); |
| ALU64_ADD (GPR[rt]); |
| ALU64_END (GPR[rd]); /* This checks for overflow. */ |
| } |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_daddi:int rt, int rs, int immediate |
| { |
| TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| { |
| ALU64_BEGIN (GPR[rs]); |
| ALU64_ADD (EXTEND16 (immediate)); |
| ALU64_END (GPR[rt]); /* This checks for overflow. */ |
| } |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| :function:::void:do_dsll32:int rd, int rt, int shift |
| { |
| int s = 32 + shift; |
| TRACE_ALU_INPUT2 (GPR[rt], s); |
| GPR[rd] = GPR[rt] << s; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_dsra32:int rd, int rt, int shift |
| { |
| int s = 32 + shift; |
| TRACE_ALU_INPUT2 (GPR[rt], s); |
| GPR[rd] = ((int64_t) GPR[rt]) >> s; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_dsrl32:int rd, int rt, int shift |
| { |
| int s = 32 + shift; |
| TRACE_ALU_INPUT2 (GPR[rt], s); |
| GPR[rd] = (uint64_t) GPR[rt] >> s; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_dsub:int rd, int rs, int rt |
| { |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| ALU64_BEGIN (GPR[rs]); |
| ALU64_SUB (GPR[rt]); |
| ALU64_END (GPR[rd]); /* This checks for overflow. */ |
| } |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_break:address_word instruction_0 |
| { |
| /* Check for some break instruction which are reserved for use by the |
| simulator. */ |
| unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; |
| if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || |
| break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) |
| { |
| sim_engine_halt (SD, CPU, NULL, cia, |
| sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
| } |
| else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || |
| break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) |
| { |
| if (STATE & simDELAYSLOT) |
| PC = cia - 4; /* reference the branch instruction */ |
| else |
| PC = cia; |
| SignalException (BreakPoint, instruction_0); |
| } |
| |
| else |
| { |
| /* If we get this far, we're not an instruction reserved by the sim. Raise |
| the exception. */ |
| SignalException (BreakPoint, instruction_0); |
| } |
| } |
| |
| :function:::void:do_break16:address_word instruction_0 |
| { |
| if (STATE & simDELAYSLOT) |
| PC = cia - 2; /* reference the branch instruction */ |
| else |
| PC = cia; |
| SignalException (BreakPoint, instruction_0); |
| } |
| |
| :function:::void:do_clo:int rd, int rs |
| { |
| uint32_t temp = GPR[rs]; |
| uint32_t i, mask; |
| if (NotWordValue (GPR[rs])) |
| Unpredictable (); |
| TRACE_ALU_INPUT1 (GPR[rs]); |
| for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) |
| { |
| if ((temp & mask) == 0) |
| break; |
| mask >>= 1; |
| } |
| GPR[rd] = EXTEND32 (i); |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_clz:int rd, int rs |
| { |
| uint32_t temp = GPR[rs]; |
| uint32_t i, mask; |
| if (NotWordValue (GPR[rs])) |
| Unpredictable (); |
| TRACE_ALU_INPUT1 (GPR[rs]); |
| for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) |
| { |
| if ((temp & mask) != 0) |
| break; |
| mask >>= 1; |
| } |
| GPR[rd] = EXTEND32 (i); |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_dclo:int rd, int rs |
| { |
| uint64_t temp = GPR[rs]; |
| uint32_t i; |
| uint64_t mask; |
| TRACE_ALU_INPUT1 (GPR[rs]); |
| for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) |
| { |
| if ((temp & mask) == 0) |
| break; |
| mask >>= 1; |
| } |
| GPR[rd] = EXTEND32 (i); |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_dclz:int rd, int rs |
| { |
| uint64_t temp = GPR[rs]; |
| uint32_t i; |
| uint64_t mask; |
| TRACE_ALU_INPUT1 (GPR[rs]); |
| for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) |
| { |
| if ((temp & mask) != 0) |
| break; |
| mask >>= 1; |
| } |
| GPR[rd] = EXTEND32 (i); |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_lb:int rt, int offset, int base |
| { |
| GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base], |
| EXTEND16 (offset))); |
| } |
| |
| :function:::void:do_lh:int rt, int offset, int base |
| { |
| GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base], |
| EXTEND16 (offset))); |
| } |
| |
| :function:::void:do_lwr:int rt, int offset, int base |
| { |
| GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base], |
| EXTEND16 (offset), GPR[rt])); |
| } |
| |
| :function:::void:do_lwl:int rt, int offset, int base |
| { |
| GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base], |
| EXTEND16 (offset), GPR[rt])); |
| } |
| |
| :function:::void:do_lwc:int num, int rt, int offset, int base |
| { |
| COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base], |
| EXTEND16 (offset))); |
| } |
| |
| :function:::void:do_lw:int rt, int offset, int base |
| { |
| GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base], |
| EXTEND16 (offset))); |
| } |
| |
| :function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0 |
| { |
| check_u64 (SD_, instruction_0); |
| GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset)); |
| } |
| |
| :function:::void:do_lhu:int rt, int offset, int base |
| { |
| GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset)); |
| } |
| |
| :function:::void:do_ldc:int num, int rt, int offset, int base |
| { |
| COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base], |
| EXTEND16 (offset))); |
| } |
| |
| :function:::void:do_lbu:int rt, int offset, int base |
| { |
| GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset)); |
| } |
| |
| :function:::void:do_ll:int rt, int insn_offset, int basereg |
| { |
| address_word base = GPR[basereg]; |
| address_word offset = EXTEND16 (insn_offset); |
| { |
| address_word vaddr = loadstore_ea (SD_, base, offset); |
| address_word paddr = vaddr; |
| if ((vaddr & 3) != 0) |
| { |
| SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, |
| sim_core_unaligned_signal); |
| } |
| else |
| { |
| uint64_t memval = 0; |
| uint64_t memval1 = 0; |
| uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| unsigned int shift = 2; |
| unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
| unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); |
| unsigned int byte; |
| paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
| LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr, |
| isDATA, isREAL); |
| byte = ((vaddr & mask) ^ (bigend << shift)); |
| GPR[rt] = EXTEND32 (memval >> (8 * byte)); |
| LLBIT = 1; |
| } |
| } |
| } |
| |
| :function:::void:do_lld:int rt, int roffset, int rbase |
| { |
| address_word base = GPR[rbase]; |
| address_word offset = EXTEND16 (roffset); |
| { |
| address_word vaddr = loadstore_ea (SD_, base, offset); |
| address_word paddr = vaddr; |
| |
| if ((vaddr & 7) != 0) |
| { |
| SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, |
| sim_core_unaligned_signal); |
| } |
| else |
| { |
| uint64_t memval = 0; |
| uint64_t memval1 = 0; |
| LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr, |
| isDATA, isREAL); |
| GPR[rt] = memval; |
| LLBIT = 1; |
| } |
| } |
| } |
| |
| :function:::void:do_lui:int rt, int immediate |
| { |
| TRACE_ALU_INPUT1 (immediate); |
| GPR[rt] = EXTEND32 (immediate << 16); |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| :function:::void:do_madd:int rs, int rt |
| { |
| int64_t temp; |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) |
| + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); |
| LO = EXTEND32 (temp); |
| HI = EXTEND32 (VH4_8 (temp)); |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_dsp_madd:int ac, int rs, int rt |
| { |
| int64_t temp; |
| if (ac == 0) |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) |
| + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); |
| DSPLO(ac) = EXTEND32 (temp); |
| DSPHI(ac) = EXTEND32 (VH4_8 (temp)); |
| if (ac == 0) |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_maddu:int rs, int rt |
| { |
| uint64_t temp; |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) |
| + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); |
| ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ |
| LO = EXTEND32 (temp); |
| HI = EXTEND32 (VH4_8 (temp)); |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_dsp_maddu:int ac, int rs, int rt |
| { |
| uint64_t temp; |
| if (ac == 0) |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) |
| + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); |
| if (ac == 0) |
| ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ |
| DSPLO(ac) = EXTEND32 (temp); |
| DSPHI(ac) = EXTEND32 (VH4_8 (temp)); |
| if (ac == 0) |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_dsp_mfhi:int ac, int rd |
| { |
| if (ac == 0) |
| do_mfhi (SD_, rd); |
| else |
| GPR[rd] = DSPHI(ac); |
| } |
| |
| :function:::void:do_dsp_mflo:int ac, int rd |
| { |
| if (ac == 0) |
| do_mflo (SD_, rd); |
| else |
| GPR[rd] = DSPLO(ac); |
| } |
| |
| :function:::void:do_movn:int rd, int rs, int rt |
| { |
| if (GPR[rt] != 0) |
| { |
| GPR[rd] = GPR[rs]; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| } |
| |
| :function:::void:do_movz:int rd, int rs, int rt |
| { |
| if (GPR[rt] == 0) |
| { |
| GPR[rd] = GPR[rs]; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| } |
| |
| :function:::void:do_msub:int rs, int rt |
| { |
| int64_t temp; |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) |
| - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); |
| LO = EXTEND32 (temp); |
| HI = EXTEND32 (VH4_8 (temp)); |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_dsp_msub:int ac, int rs, int rt |
| { |
| int64_t temp; |
| if (ac == 0) |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) |
| - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); |
| DSPLO(ac) = EXTEND32 (temp); |
| DSPHI(ac) = EXTEND32 (VH4_8 (temp)); |
| if (ac == 0) |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_msubu:int rs, int rt |
| { |
| uint64_t temp; |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) |
| - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); |
| LO = EXTEND32 (temp); |
| HI = EXTEND32 (VH4_8 (temp)); |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_dsp_msubu:int ac, int rs, int rt |
| { |
| uint64_t temp; |
| if (ac == 0) |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) |
| - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); |
| DSPLO(ac) = EXTEND32 (temp); |
| DSPHI(ac) = EXTEND32 (VH4_8 (temp)); |
| if (ac == 0) |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_mthi:int rs |
| { |
| check_mt_hilo (SD_, HIHISTORY); |
| HI = GPR[rs]; |
| } |
| |
| :function:::void:do_dsp_mthi:int ac, int rs |
| { |
| if (ac == 0) |
| check_mt_hilo (SD_, HIHISTORY); |
| DSPHI(ac) = GPR[rs]; |
| } |
| |
| :function:::void:do_mtlo:int rs |
| { |
| check_mt_hilo (SD_, LOHISTORY); |
| LO = GPR[rs]; |
| } |
| |
| :function:::void:do_dsp_mtlo:int ac, int rs |
| { |
| if (ac == 0) |
| check_mt_hilo (SD_, LOHISTORY); |
| DSPLO(ac) = GPR[rs]; |
| } |
| |
| :function:::void:do_mul:int rd, int rs, int rt |
| { |
| int64_t prod; |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| prod = (((int64_t)(int32_t) GPR[rs]) |
| * ((int64_t)(int32_t) GPR[rt])); |
| GPR[rd] = EXTEND32 (VL4_8 (prod)); |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_dsp_mult:int ac, int rs, int rt |
| { |
| int64_t prod; |
| if (ac == 0) |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| prod = ((int64_t)(int32_t) GPR[rs]) |
| * ((int64_t)(int32_t) GPR[rt]); |
| DSPLO(ac) = EXTEND32 (VL4_8 (prod)); |
| DSPHI(ac) = EXTEND32 (VH4_8 (prod)); |
| if (ac == 0) |
| { |
| ACX = 0; /* SmartMIPS */ |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| } |
| |
| :function:::void:do_dsp_multu:int ac, int rs, int rt |
| { |
| uint64_t prod; |
| if (ac == 0) |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| prod = ((uint64_t)(uint32_t) GPR[rs]) |
| * ((uint64_t)(uint32_t) GPR[rt]); |
| DSPLO(ac) = EXTEND32 (VL4_8 (prod)); |
| DSPHI(ac) = EXTEND32 (VH4_8 (prod)); |
| if (ac == 0) |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_pref:int hint, int insn_offset, int insn_base |
| { |
| /* |
| address_word base = GPR[insn_base]; |
| address_word offset = EXTEND16 (insn_offset); |
| address_word vaddr = loadstore_ea (SD_, base, offset); |
| address_word paddr = vaddr; |
| Prefetch (paddr, vaddr, isDATA, hint); |
| */ |
| } |
| |
| :function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit |
| { |
| address_word base = GPR[basereg]; |
| address_word offset = EXTEND16 (offsetarg); |
| { |
| address_word vaddr = loadstore_ea (SD_, base, offset); |
| address_word paddr = vaddr; |
| |
| if ((vaddr & 3) != 0) |
| { |
| SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, |
| sim_core_unaligned_signal); |
| } |
| else |
| { |
| uint64_t memval = 0; |
| uint64_t memval1 = 0; |
| uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| address_word reverseendian = |
| (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); |
| address_word bigendiancpu = |
| (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); |
| unsigned int byte; |
| paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); |
| byte = ((vaddr & mask) ^ bigendiancpu); |
| memval = ((uint64_t) GPR[rt] << (8 * byte)); |
| if (LLBIT) |
| StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, |
| isREAL); |
| if (store_ll_bit) |
| GPR[rt] = LLBIT; |
| } |
| } |
| } |
| |
| :function:::void:do_scd:int rt, int roffset, int rbase, int store_ll_bit |
| { |
| address_word base = GPR[rbase]; |
| address_word offset = EXTEND16 (roffset); |
| { |
| address_word vaddr = loadstore_ea (SD_, base, offset); |
| address_word paddr = vaddr; |
| |
| if ((vaddr & 7) != 0) |
| { |
| SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, |
| sim_core_unaligned_signal); |
| } |
| else |
| { |
| uint64_t memval = 0; |
| uint64_t memval1 = 0; |
| memval = GPR[rt]; |
| if (LLBIT) |
| StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr, |
| isREAL); |
| if (store_ll_bit) |
| GPR[rt] = LLBIT; |
| } |
| } |
| } |
| |
| :function:::void:do_sub:int rs, int rt, int rd |
| { |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| ALU32_BEGIN (GPR[rs]); |
| ALU32_SUB (GPR[rt]); |
| ALU32_END (GPR[rd]); /* This checks for overflow. */ |
| } |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| :function:::void:do_sw:int rt, int offset, int base |
| { |
| do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]); |
| } |
| |
| :function:::void:do_teq:int rs, int rt, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] == (signed_word) GPR[rt]) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_teqi:int rs, int immediate, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate)) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tge:int rs, int rt, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] >= (signed_word) GPR[rt]) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tgei:int rs, int immediate, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate)) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tgeiu:int rs, int immediate, address_word instruction_0 |
| { |
| if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate)) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tgeu:int rs ,int rt, address_word instruction_0 |
| { |
| if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt]) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tlt:int rs, int rt, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] < (signed_word) GPR[rt]) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tlti:int rs, int immediate, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tltiu:int rs, int immediate, address_word instruction_0 |
| { |
| if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tltu:int rs, int rt, address_word instruction_0 |
| { |
| if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tne:int rs, int rt, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] != (signed_word) GPR[rt]) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_tnei:int rs, int immediate, address_word instruction_0 |
| { |
| if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate)) |
| SignalException (Trap, instruction_0); |
| } |
| |
| :function:::void:do_abs_fmt:int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt)); |
| } |
| |
| :function:::void:do_add_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); |
| } |
| |
| :function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0 |
| { |
| uint64_t fsx; |
| uint64_t ftx; |
| uint64_t fdx; |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| fsx = ValueFPR (fs, fmt_ps); |
| if ((GPR[rs] & 0x3) != 0) |
| Unpredictable (); |
| if ((GPR[rs] & 0x4) == 0) |
| fdx = fsx; |
| else |
| { |
| ftx = ValueFPR (ft, fmt_ps); |
| if (BigEndianCPU) |
| fdx = PackPS (PSLower (fsx), PSUpper (ftx)); |
| else |
| fdx = PackPS (PSLower (ftx), PSUpper (fsx)); |
| } |
| StoreFPR (fd, fmt_ps, fdx); |
| } |
| |
| :function:::void:do_c_cond_fmt:int cond, int fmt, int cc, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc); |
| TRACE_ALU_RESULT (ValueFCR (31)); |
| } |
| |
| :function:::void:do_ceil_fmt:int type, int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt, |
| type)); |
| } |
| |
| :function:::void:do_cfc1:int rt, int fs |
| { |
| check_fpu (SD_); |
| if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31) |
| { |
| unsigned_word fcr = ValueFCR (fs); |
| TRACE_ALU_INPUT1 (fcr); |
| GPR[rt] = fcr; |
| } |
| /* else NOP */ |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| :function:::void:do_ctc1:int rt, int fs |
| { |
| check_fpu (SD_); |
| TRACE_ALU_INPUT1 (GPR[rt]); |
| if (fs == 25 || fs == 26 || fs == 28 || fs == 31) |
| StoreFCR (fs, GPR[rt]); |
| /* else NOP */ |
| } |
| |
| :function:::void:do_cvt_d_fmt:int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| if ((fmt == fmt_double) | 0) |
| SignalException (ReservedInstruction, instruction_0); |
| StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt, |
| fmt_double)); |
| } |
| |
| :function:::void:do_cvt_l_fmt:int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) |
| SignalException (ReservedInstruction, instruction_0); |
| StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt, |
| fmt_long)); |
| } |
| |
| :function:::void:do_cvt_ps_s:int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single), |
| ValueFPR (ft, fmt_single))); |
| } |
| |
| :function:::void:do_cvt_s_fmt:int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| if ((fmt == fmt_single) | 0) |
| SignalException (ReservedInstruction, instruction_0); |
| StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt, |
| fmt_single)); |
| } |
| |
| :function:::void:do_cvt_s_pl:int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps))); |
| } |
| |
| :function:::void:do_cvt_s_pu:int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps))); |
| } |
| |
| :function:::void:do_cvt_w_fmt:int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) |
| SignalException (ReservedInstruction, instruction_0); |
| StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt, |
| fmt_word)); |
| } |
| |
| :function:::void:do_div_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); |
| } |
| |
| :function:::void:do_dmfc1b:int rt, int fs |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| *micromips64: |
| { |
| if (SizeFGR () == 64) |
| GPR[rt] = FGR[fs]; |
| else if ((fs & 0x1) == 0) |
| GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs]; |
| else |
| Unpredictable (); |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| :function:::void:do_dmtc1b:int rt, int fs |
| { |
| if (SizeFGR () == 64) |
| StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]); |
| else if ((fs & 0x1) == 0) |
| StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]); |
| else |
| Unpredictable (); |
| } |
| |
| :function:::void:do_floor_fmt:int type, int fmt, int fd, int fs |
| { |
| check_fpu (SD_); |
| StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt, |
| type)); |
| } |
| |
| :function:::void:do_luxc1_32:int fd, int rindex, int rbase |
| *mips32r2: |
| *micromips32: |
| { |
| address_word base = GPR[rbase]; |
| address_word index = GPR[rindex]; |
| address_word vaddr = base + index; |
| check_fpu (SD_); |
| if (SizeFGR () != 64) |
| Unpredictable (); |
| /* Arrange for the bottom 3 bits of (base + index) to be 0. */ |
| if ((vaddr & 0x7) != 0) |
| index -= (vaddr & 0x7); |
| COP_LD (1, fd, do_load_double (SD_, base, index)); |
| } |
| |
| :function:::void:do_luxc1_64:int fd, int rindex, int rbase |
| { |
| address_word base = GPR[rbase]; |
| address_word index = GPR[rindex]; |
| address_word vaddr = base + index; |
| if (SizeFGR () != 64) |
| Unpredictable (); |
| /* Arrange for the bottom 3 bits of (base + index) to be 0. */ |
| if ((vaddr & 0x7) != 0) |
| index -= (vaddr & 0x7); |
| COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index)); |
| |
| } |
| |
| :function:::void:do_lwc1:int ft, int offset, int base |
| { |
| check_fpu (SD_); |
| COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base], |
| EXTEND16 (offset))); |
| } |
| |
| :function:::void:do_lwxc1:int fd, int index, int base, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index])); |
| } |
| |
| :function:::void:do_madd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt), |
| ValueFPR (fr, fmt), fmt)); |
| } |
| |
| :function:::void:do_mfc1b:int rt, int fs |
| { |
| check_fpu (SD_); |
| GPR[rt] = EXTEND32 (FGR[fs]); |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| :function:::void:do_mov_fmt:int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, ValueFPR (fs, fmt)); |
| } |
| |
| :function:::void:do_movtf:int tf, int rd, int rs, int cc |
| { |
| check_fpu (SD_); |
| if (GETFCC(cc) == tf) |
| GPR[rd] = GPR[rs]; |
| } |
| |
| :function:::void:do_movtf_fmt:int tf, int fmt, int fd, int fs, int cc |
| { |
| check_fpu (SD_); |
| if (fmt != fmt_ps) |
| { |
| if (GETFCC(cc) == tf) |
| StoreFPR (fd, fmt, ValueFPR (fs, fmt)); |
| else |
| StoreFPR (fd, fmt, ValueFPR (fd, fmt)); /* set fmt */ |
| } |
| else |
| { |
| uint64_t fdx; |
| fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd, |
| fmt_ps)), |
| PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd, |
| fmt_ps))); |
| StoreFPR (fd, fmt_ps, fdx); |
| } |
| } |
| |
| :function:::void:do_movn_fmt:int fmt, int fd, int fs, int rt |
| { |
| check_fpu (SD_); |
| if (GPR[rt] != 0) |
| StoreFPR (fd, fmt, ValueFPR (fs, fmt)); |
| else |
| StoreFPR (fd, fmt, ValueFPR (fd, fmt)); |
| } |
| |
| :function:::void:do_movz_fmt:int fmt, int fd, int fs, int rt |
| { |
| check_fpu (SD_); |
| if (GPR[rt] == 0) |
| StoreFPR (fd, fmt, ValueFPR (fs, fmt)); |
| else |
| StoreFPR (fd, fmt, ValueFPR (fd, fmt)); |
| } |
| |
| :function:::void:do_msub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), |
| ValueFPR (fr, fmt), fmt)); |
| } |
| |
| :function:::void:do_mtc1b:int rt, int fs |
| { |
| check_fpu (SD_); |
| StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt])); |
| } |
| |
| :function:::void:do_mul_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); |
| } |
| |
| :function:::void:do_neg_fmt:int fmt, int fd, int fs, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt)); |
| } |
| |
| :function:::void:do_nmadd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt), |
| ValueFPR (fr, fmt), fmt)); |
| } |
| |
| :function:::void:do_nmsub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), |
| ValueFPR (fr, fmt), fmt)); |
| } |
| |
| :function:::void:do_pll_ps:int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)), |
| PSLower (ValueFPR (ft, fmt_ps)))); |
| } |
| |
| :function:::void:do_plu_ps:int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)), |
| PSUpper (ValueFPR (ft, fmt_ps)))); |
| } |
| |
| :function:::void:do_pul_ps:int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)), |
| PSLower (ValueFPR (ft, fmt_ps)))); |
| } |
| |
| :function:::void:do_puu_ps:int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)), |
| PSUpper (ValueFPR (ft, fmt_ps)))); |
| } |
| |
| :function:::void:do_recip_fmt:int fmt, int fd, int fs |
| { |
| check_fpu (SD_); |
| StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt)); |
| } |
| |
| :function:::void:do_round_fmt:int type, int fmt, int fd, int fs |
| { |
| check_fpu (SD_); |
| StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt, |
| type)); |
| } |
| |
| :function:::void:do_rsqrt_fmt:int fmt, int fd, int fs |
| { |
| check_fpu (SD_); |
| StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt)); |
| } |
| |
| :function:::void:do_prefx:int hint, int rindex, int rbase |
| { |
| /* |
| address_word base = GPR[rbase]; |
| address_word index = GPR[rindex]; |
| address_word vaddr = loadstore_ea (SD_, base, index); |
| address_word paddr = vaddr; |
| Prefetch (paddr, vaddr, isDATA, hint); |
| */ |
| } |
| |
| :function:::void:do_sdc1:int ft, int offset, int base |
| *mipsII: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *micromips32: |
| { |
| check_fpu (SD_); |
| do_store_double (SD_, GPR[base], EXTEND16 (offset), COP_SD (1, ft)); |
| } |
| |
| :function:::void:do_suxc1_32:int fs, int rindex, int rbase |
| *mips32r2: |
| *micromips32: |
| { |
| address_word base = GPR[rbase]; |
| address_word index = GPR[rindex]; |
| address_word vaddr = base + index; |
| check_fpu (SD_); |
| if (SizeFGR () != 64) |
| Unpredictable (); |
| /* Arrange for the bottom 3 bits of (base + index) to be 0. */ |
| if ((vaddr & 0x7) != 0) |
| index -= (vaddr & 0x7); |
| do_store_double (SD_, base, index, COP_SD (1, fs)); |
| } |
| |
| :function:::void:do_suxc1_64:int fs, int rindex, int rbase |
| { |
| address_word base = GPR[rbase]; |
| address_word index = GPR[rindex]; |
| address_word vaddr = base + index; |
| if (SizeFGR () != 64) |
| Unpredictable (); |
| /* Arrange for the bottom 3 bits of (base + index) to be 0. */ |
| if ((vaddr & 0x7) != 0) |
| index -= (vaddr & 0x7); |
| do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs)); |
| } |
| |
| :function:::void:do_sqrt_fmt:int fmt, int fd, int fs |
| { |
| check_fpu (SD_); |
| StoreFPR (fd, fmt, (SquareRoot (ValueFPR (fs, fmt), fmt))); |
| } |
| |
| :function:::void:do_sub_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 |
| { |
| check_fpu (SD_); |
| check_fmt_p (SD_, fmt, instruction_0); |
| StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); |
| } |
| |
| :function:::void:do_swc1:int ft, int roffset, int rbase, address_word instruction_0 |
| { |
| address_word base = GPR[rbase]; |
| address_word offset = EXTEND16 (roffset); |
| check_fpu (SD_); |
| { |
| address_word vaddr = loadstore_ea (SD_, base, offset); |
| address_word paddr = vaddr; |
| |
| if ((vaddr & 3) != 0) |
| { |
| SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, |
| write_transfer, sim_core_unaligned_signal); |
| } |
| else |
| { |
| uword64 memval = 0; |
| uword64 memval1 = 0; |
| uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| address_word reverseendian = |
| (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); |
| address_word bigendiancpu = |
| (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); |
| unsigned int byte; |
| paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); |
| byte = ((vaddr & mask) ^ bigendiancpu); |
| memval = (((uword64)COP_SW(1, ft)) << (8 * byte)); |
| StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL); |
| } |
| } |
| } |
| |
| :function:::void:do_swxc1:int fs, int rindex, int rbase, address_word instruction_0 |
| { |
| address_word base = GPR[rbase]; |
| address_word index = GPR[rindex]; |
| check_fpu (SD_); |
| check_u64 (SD_, instruction_0); |
| { |
| address_word vaddr = loadstore_ea (SD_, base, index); |
| address_word paddr = vaddr; |
| |
| if ((vaddr & 3) != 0) |
| { |
| SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, |
| sim_core_unaligned_signal); |
| } |
| else |
| { |
| uint64_t memval = 0; |
| uint64_t memval1 = 0; |
| uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| address_word reverseendian = |
| (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); |
| address_word bigendiancpu = |
| (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); |
| unsigned int byte; |
| paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); |
| byte = ((vaddr & mask) ^ bigendiancpu); |
| memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte)); |
| StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, |
| isREAL); |
| } |
| } |
| } |
| |
| :function:::void:do_trunc_fmt:int type, int fmt, int fd, int fs |
| { |
| check_fpu (SD_); |
| StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt, |
| type)); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD |
| "add r<RD>, r<RS>, r<RT>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_add (SD_, RS, RT, RD); |
| } |
| |
| |
| |
| 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI |
| "addi r<RT>, r<RS>, <IMMEDIATE>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_addi (SD_, RS, RT, IMMEDIATE); |
| } |
| |
| |
| |
| :function:::void:do_addiu:int rs, int rt, uint16_t immediate |
| { |
| if (NotWordValue (GPR[rs])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU |
| "addiu r<RT>, r<RS>, <IMMEDIATE>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_addiu (SD_, RS, RT, IMMEDIATE); |
| } |
| |
| |
| |
| :function:::void:do_addu:int rs, int rt, int rd |
| { |
| if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
| Unpredictable (); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU |
| "addu r<RD>, r<RS>, r<RT>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_addu (SD_, RS, RT, RD); |
| } |
| |
| |
| |
| :function:::void:do_and:int rs, int rt, int rd |
| { |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| GPR[rd] = GPR[rs] & GPR[rt]; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND |
| "and r<RD>, r<RS>, r<RT>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_and (SD_, RS, RT, RD); |
| } |
| |
| |
| |
| 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI |
| "andi r<RT>, r<RS>, %#lx<IMMEDIATE>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_andi (SD_,RS, RT, IMMEDIATE); |
| } |
| |
| |
| |
| 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ |
| "beq r<RS>, r<RT>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| |
| 000100,5.RS,5.RT,16.OFFSET:R6:32::BEQ |
| "beq r<RS>, r<RT>, <OFFSET>" |
| *mips32r6: |
| *mips64r6: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if (GPR[RS] == GPR[RT]) |
| DELAY_SLOT (NIA + offset); |
| else |
| FORBIDDEN_SLOT (); |
| } |
| |
| 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL |
| "beql r<RS>, r<RT>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ |
| "bgez r<RS>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] >= 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| |
| |
| 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL |
| "bgezal r<RS>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if (RS == 31) |
| Unpredictable (); |
| RA = (CIA + 8); |
| if ((signed_word) GPR[RS] >= 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| 000001,00000,10001,16.OFFSET:REGIMM:32::BAL |
| "bal <OFFSET>" |
| *mips32r6: |
| *mips64r6: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| RA = (CIA + 8); |
| DELAY_SLOT (NIA + offset); |
| } |
| |
| 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL |
| "bgezall r<RS>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if (RS == 31) |
| Unpredictable (); |
| RA = (CIA + 8); |
| /* NOTE: The branch occurs AFTER the next instruction has been |
| executed */ |
| if ((signed_word) GPR[RS] >= 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL |
| "bgezl r<RS>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] >= 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ |
| "bgtz r<RS>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] > 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| |
| |
| 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL |
| "bgtzl r<RS>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| /* NOTE: The branch occurs AFTER the next instruction has been |
| executed */ |
| if ((signed_word) GPR[RS] > 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ |
| "blez r<RS>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| /* NOTE: The branch occurs AFTER the next instruction has been |
| executed */ |
| if ((signed_word) GPR[RS] <= 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| |
| |
| 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL |
| "bgezl r<RS>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] <= 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ |
| "bltz r<RS>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] < 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| |
| |
| 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL |
| "bltzal r<RS>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if (RS == 31) |
| Unpredictable (); |
| RA = (CIA + 8); |
| /* NOTE: The branch occurs AFTER the next instruction has been |
| executed */ |
| if ((signed_word) GPR[RS] < 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| |
| |
| 000001,00000,10000,16.OFFSET:REGIMM:32::NAL |
| "nal <OFFSET>" |
| *mips32r6: |
| *mips64r6: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| RA = (CIA + 8); |
| FORBIDDEN_SLOT (); |
| } |
| |
| |
| |
| 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL |
| "bltzall r<RS>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if (RS == 31) |
| Unpredictable (); |
| RA = (CIA + 8); |
| if ((signed_word) GPR[RS] < 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL |
| "bltzl r<RS>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| /* NOTE: The branch occurs AFTER the next instruction has been |
| executed */ |
| if ((signed_word) GPR[RS] < 0) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE |
| "bne r<RS>, r<RT>, <OFFSET>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| } |
| |
| |
| |
| 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL |
| "bnel r<RS>, r<RT>, <OFFSET>" |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| address_word offset = EXTEND16 (OFFSET) << 2; |
| if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
| { |
| DELAY_SLOT (NIA + offset); |
| } |
| else |
| NULLIFY_NEXT_INSTRUCTION (); |
| } |
| |
| |
| |
| 000000,20.CODE,001101:SPECIAL:32::BREAK |
| "break %#lx<CODE>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips32r6: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_break (SD_, instruction_0); |
| } |
| |
| |
| |
| 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO |
| "clo r<RD>, r<RS>" |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr5500: |
| { |
| if (RT != RD) |
| Unpredictable (); |
| do_clo (SD_, RD, RS); |
| } |
| |
| |
| |
| 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ |
| "clz r<RD>, r<RS>" |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr5500: |
| { |
| if (RT != RD) |
| Unpredictable (); |
| do_clz (SD_, RD, RS); |
| } |
| |
| |
| |
| 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD |
| "dadd r<RD>, r<RS>, r<RT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dadd (SD_, RD, RS, RT); |
| } |
| |
| |
| |
| 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI |
| "daddi r<RT>, r<RS>, <IMMEDIATE>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_daddi (SD_, RT, RS, IMMEDIATE); |
| } |
| |
| |
| |
| :function:::void:do_daddiu:int rs, int rt, uint16_t immediate |
| { |
| TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| GPR[rt] = GPR[rs] + EXTEND16 (immediate); |
| TRACE_ALU_RESULT (GPR[rt]); |
| } |
| |
| 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU |
| "daddiu r<RT>, r<RS>, <IMMEDIATE>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_daddiu (SD_, RS, RT, IMMEDIATE); |
| } |
| |
| |
| |
| :function:::void:do_daddu:int rs, int rt, int rd |
| { |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| GPR[rd] = GPR[rs] + GPR[rt]; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU |
| "daddu r<RD>, r<RS>, r<RT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_daddu (SD_, RS, RT, RD); |
| } |
| |
| |
| |
| 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO |
| "dclo r<RD>, r<RS>" |
| *mips64: |
| *mips64r2: |
| *vr5500: |
| { |
| if (RT != RD) |
| Unpredictable (); |
| check_u64 (SD_, instruction_0); |
| if (RT != RD) |
| Unpredictable (); |
| do_dclo (SD_, RD, RS); |
| } |
| |
| |
| |
| 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ |
| "dclz r<RD>, r<RS>" |
| *mips64: |
| *mips64r2: |
| *vr5500: |
| { |
| if (RT != RD) |
| Unpredictable (); |
| check_u64 (SD_, instruction_0); |
| if (RT != RD) |
| Unpredictable (); |
| do_dclz (SD_, RD, RS); |
| } |
| |
| |
| |
| :function:::void:do_ddiv:int rs, int rt |
| { |
| check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| int64_t n = GPR[rs]; |
| int64_t d = GPR[rt]; |
| int64_t hi; |
| int64_t lo; |
| if (d == 0) |
| { |
| lo = SIGNED64 (0x8000000000000000); |
| hi = 0; |
| } |
| else if (d == -1 && n == SIGNED64 (0x8000000000000000)) |
| { |
| lo = SIGNED64 (0x8000000000000000); |
| hi = 0; |
| } |
| else |
| { |
| lo = (n / d); |
| hi = (n % d); |
| } |
| HI = hi; |
| LO = lo; |
| } |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV |
| "ddiv r<RS>, r<RT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_ddiv (SD_, RS, RT); |
| } |
| |
| |
| |
| :function:::void:do_ddivu:int rs, int rt |
| { |
| check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| uint64_t n = GPR[rs]; |
| uint64_t d = GPR[rt]; |
| uint64_t hi; |
| uint64_t lo; |
| if (d == 0) |
| { |
| lo = SIGNED64 (0x8000000000000000); |
| hi = 0; |
| } |
| else |
| { |
| lo = (n / d); |
| hi = (n % d); |
| } |
| HI = hi; |
| LO = lo; |
| } |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU |
| "ddivu r<RS>, r<RT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_ddivu (SD_, RS, RT); |
| } |
| |
| :function:::void:do_div:int rs, int rt |
| { |
| check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| int32_t n = GPR[rs]; |
| int32_t d = GPR[rt]; |
| if (d == 0) |
| { |
| LO = EXTEND32 (0x80000000); |
| HI = EXTEND32 (0); |
| } |
| else if (n == SIGNED32 (0x80000000) && d == -1) |
| { |
| LO = EXTEND32 (0x80000000); |
| HI = EXTEND32 (0); |
| } |
| else |
| { |
| LO = EXTEND32 (n / d); |
| HI = EXTEND32 (n % d); |
| } |
| } |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV |
| "div r<RS>, r<RT>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_div (SD_, RS, RT); |
| } |
| |
| |
| |
| :function:::void:do_divu:int rs, int rt |
| { |
| check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| { |
| uint32_t n = GPR[rs]; |
| uint32_t d = GPR[rt]; |
| if (d == 0) |
| { |
| LO = EXTEND32 (0x80000000); |
| HI = EXTEND32 (0); |
| } |
| else |
| { |
| LO = EXTEND32 (n / d); |
| HI = EXTEND32 (n % d); |
| } |
| } |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU |
| "divu r<RS>, r<RT>" |
| *mipsI: |
| *mipsII: |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips32: |
| *mips32r2: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| *vr5000: |
| *r3900: |
| { |
| do_divu (SD_, RS, RT); |
| } |
| |
| |
| :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p |
| { |
| uint64_t lo; |
| uint64_t hi; |
| uint64_t m00; |
| uint64_t m01; |
| uint64_t m10; |
| uint64_t m11; |
| uint64_t mid; |
| int sign; |
| uint64_t op1 = GPR[rs]; |
| uint64_t op2 = GPR[rt]; |
| check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| /* make signed multiply unsigned */ |
| sign = 0; |
| if (signed_p) |
| { |
| if ((int64_t) op1 < 0) |
| { |
| op1 = - op1; |
| ++sign; |
| } |
| if ((int64_t) op2 < 0) |
| { |
| op2 = - op2; |
| ++sign; |
| } |
| } |
| /* multiply out the 4 sub products */ |
| m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2)); |
| m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2)); |
| m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2)); |
| m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2)); |
| /* add the products */ |
| mid = ((uint64_t) VH4_8 (m00) |
| + (uint64_t) VL4_8 (m10) |
| + (uint64_t) VL4_8 (m01)); |
| lo = U8_4 (mid, m00); |
| hi = (m11 |
| + (uint64_t) VH4_8 (mid) |
| + (uint64_t) VH4_8 (m01) |
| + (uint64_t) VH4_8 (m10)); |
| /* fix the sign */ |
| if (sign & 1) |
| { |
| lo = -lo; |
| if (lo == 0) |
| hi = -hi; |
| else |
| hi = -hi - 1; |
| } |
| /* save the result HI/LO (and a gpr) */ |
| LO = lo; |
| HI = hi; |
| if (rd != 0) |
| GPR[rd] = lo; |
| TRACE_ALU_RESULT2 (HI, LO); |
| } |
| |
| :function:::void:do_dmult:int rs, int rt, int rd |
| { |
| do_dmultx (SD_, rs, rt, rd, 1); |
| } |
| |
| 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT |
| "dmult r<RS>, r<RT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dmult (SD_, RS, RT, 0); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT |
| "dmult r<RS>, r<RT>":RD == 0 |
| "dmult r<RD>, r<RS>, r<RT>" |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dmult (SD_, RS, RT, RD); |
| } |
| |
| |
| |
| :function:::void:do_dmultu:int rs, int rt, int rd |
| { |
| do_dmultx (SD_, rs, rt, rd, 0); |
| } |
| |
| 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU |
| "dmultu r<RS>, r<RT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *vr4100: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dmultu (SD_, RS, RT, 0); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU |
| "dmultu r<RD>, r<RS>, r<RT>":RD == 0 |
| "dmultu r<RS>, r<RT>" |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dmultu (SD_, RS, RT, RD); |
| } |
| |
| |
| :function:::uint64_t:do_dror:uint64_t x,uint64_t y |
| { |
| uint64_t result; |
| |
| y &= 63; |
| TRACE_ALU_INPUT2 (x, y); |
| result = ROTR64 (x, y); |
| TRACE_ALU_RESULT (result); |
| return result; |
| } |
| |
| 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR |
| "dror r<RD>, r<RT>, <SHIFT>" |
| *mips64r2: |
| *mips64r6: |
| *vr5400: |
| *vr5500: |
| { |
| check_u64 (SD_, instruction_0); |
| GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); |
| } |
| |
| 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 |
| "dror32 r<RD>, r<RT>, <SHIFT>" |
| *mips64r2: |
| *mips64r6: |
| *vr5400: |
| *vr5500: |
| { |
| check_u64 (SD_, instruction_0); |
| GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV |
| "drorv r<RD>, r<RT>, r<RS>" |
| *mips64r2: |
| *mips64r6: |
| *vr5400: |
| *vr5500: |
| { |
| check_u64 (SD_, instruction_0); |
| GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); |
| } |
| |
| |
| :function:::void:do_dsll:int rt, int rd, int shift |
| { |
| TRACE_ALU_INPUT2 (GPR[rt], shift); |
| GPR[rd] = GPR[rt] << shift; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL |
| "dsll r<RD>, r<RT>, <SHIFT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dsll (SD_, RT, RD, SHIFT); |
| } |
| |
| |
| 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 |
| "dsll32 r<RD>, r<RT>, <SHIFT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dsll32 (SD_, RD, RT, SHIFT); |
| } |
| |
| :function:::void:do_dsllv:int rs, int rt, int rd |
| { |
| int s = MASKED64 (GPR[rs], 5, 0); |
| TRACE_ALU_INPUT2 (GPR[rt], s); |
| GPR[rd] = GPR[rt] << s; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV |
| "dsllv r<RD>, r<RT>, r<RS>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dsllv (SD_, RS, RT, RD); |
| } |
| |
| :function:::void:do_dsra:int rt, int rd, int shift |
| { |
| TRACE_ALU_INPUT2 (GPR[rt], shift); |
| GPR[rd] = ((int64_t) GPR[rt]) >> shift; |
| TRACE_ALU_RESULT (GPR[rd]); |
| } |
| |
| |
| 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA |
| "dsra r<RD>, r<RT>, <SHIFT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dsra (SD_, RT, RD, SHIFT); |
| } |
| |
| |
| 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 |
| "dsra32 r<RD>, r<RT>, <SHIFT>" |
| *mipsIII: |
| *mipsIV: |
| *mipsV: |
| *mips64: |
| *mips64r2: |
| *mips64r6: |
| *vr4100: |
| *vr5000: |
| { |
| check_u64 (SD_, instruction_0); |
| do_dsra32 (SD_, RD, RT, SHIFT); |
| } |
| |
| |
| :function:::void:do_dsrav:int rs, int rt, int rd |
| { |
| int s = MASKED64 (GPR[rs], 5, 0); |
| TRACE_ALU_INPUT2 (GPR[
|
