//Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp | |
// Spec Reference: alu2op divide s | |
# mach: bfin | |
.include "testutils.inc" | |
start | |
imm32 r0, 0x00000000; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0x23456789; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x856789ab; | |
imm32 r5, 0x96789abc; | |
imm32 r6, 0xa789abcd; | |
imm32 r7, 0xb89abcde; | |
R0.L = 1; | |
DIVS ( R1 , R0 ); | |
DIVS ( R2 , R0 ); | |
DIVS ( R3 , R0 ); | |
DIVS ( R4 , R0 ); | |
DIVS ( R5 , R0 ); | |
DIVS ( R6 , R0 ); | |
DIVS ( R7 , R0 ); | |
DIVS ( R4 , R0 ); | |
DIVS ( R0 , R0 ); | |
CHECKREG r1, 0x2468ACF0; | |
CHECKREG r2, 0x468ACF12; | |
CHECKREG r3, 0x68ACF134; | |
CHECKREG r4, 0x159E26AE; | |
CHECKREG r5, 0x2CF13579; | |
CHECKREG r6, 0x4F13579B; | |
CHECKREG r7, 0x713579BD; | |
CHECKREG r0, 0x00000002; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x00000000; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0xa456789a; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0xc6789abc; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0xe89abcde; | |
R1.L = -1; | |
DIVS ( R0 , R1 ); | |
DIVS ( R2 , R1 ); | |
DIVS ( R3 , R1 ); | |
DIVS ( R4 , R1 ); | |
DIVS ( R5 , R1 ); | |
DIVS ( R6 , R1 ); | |
DIVS ( R7 , R1 ); | |
DIVS ( R1 , R1 ); | |
CHECKREG r0, 0x02460005; | |
CHECKREG r1, 0x0001FFFF; | |
CHECKREG r2, 0x268ACF12; | |
CHECKREG r3, 0x48ACF134; | |
CHECKREG r4, 0x6ACF1356; | |
CHECKREG r5, 0x8CF13578; | |
CHECKREG r6, 0xAF13579A; | |
CHECKREG r7, 0xD13579BC; | |
imm32 r0, 0x51230002; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0x00000000; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x956789ab; | |
imm32 r5, 0x86789abc; | |
imm32 r6, 0x6789abcd; | |
imm32 r7, 0x789abcde; | |
R2.L = 31; | |
DIVS ( R0 , R2 ); | |
DIVS ( R1 , R2 ); | |
DIVS ( R3 , R2 ); | |
DIVS ( R4 , R2 ); | |
DIVS ( R5 , R2 ); | |
DIVS ( R6 , R2 ); | |
DIVS ( R7 , R2 ); | |
DIVS ( R2 , R2 ); | |
CHECKREG r0, 0xA2460004; | |
CHECKREG r1, 0x2468ACF0; | |
CHECKREG r2, 0x0000003E; | |
CHECKREG r3, 0x68ACF134; | |
CHECKREG r4, 0x2ACF1357; | |
CHECKREG r5, 0x0CF13579; | |
CHECKREG r6, 0xCF13579A; | |
CHECKREG r7, 0xF13579BC; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x82345678; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0x00000000; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0xc6789abc; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0xe89abcde; | |
R3.L = -31; | |
DIVS ( R0 , R3 ); | |
DIVS ( R1 , R3 ); | |
DIVS ( R2 , R3 ); | |
DIVS ( R4 , R3 ); | |
DIVS ( R5 , R3 ); | |
DIVS ( R6 , R3 ); | |
DIVS ( R7 , R3 ); | |
DIVS ( R3 , R3 ); | |
CHECKREG r0, 0x02460005; | |
CHECKREG r1, 0x0468ACF0; | |
CHECKREG r2, 0x268ACF12; | |
CHECKREG r3, 0x0001FFC3; | |
CHECKREG r4, 0x6ACF1356; | |
CHECKREG r5, 0x8CF13578; | |
CHECKREG r6, 0xAF13579A; | |
CHECKREG r7, 0xD13579BC; | |
imm32 r0, 0x00000001; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0x23456789; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x00000000; | |
imm32 r5, 0x96789abc; | |
imm32 r6, 0xa789abcd; | |
imm32 r7, 0xb89abcde; | |
R4.L = 15; | |
DIVS ( R1 , R4 ); | |
DIVS ( R2 , R4 ); | |
DIVS ( R3 , R4 ); | |
DIVS ( R0 , R4 ); | |
DIVS ( R5 , R4 ); | |
DIVS ( R6 , R4 ); | |
DIVS ( R7 , R4 ); | |
DIVS ( R4 , R4 ); | |
CHECKREG r0, 0x00000002; | |
CHECKREG r1, 0x2468ACF0; | |
CHECKREG r2, 0x468ACF12; | |
CHECKREG r3, 0x68ACF134; | |
CHECKREG r4, 0x0000001E; | |
CHECKREG r5, 0x2CF13579; | |
CHECKREG r6, 0x4F13579B; | |
CHECKREG r7, 0x713579BD; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x00000000; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0xa456789a; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0x00000000; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0xe89abcde; | |
R5.L = -15; | |
DIVS ( R0 , R5 ); | |
DIVS ( R1 , R5 ); | |
DIVS ( R2 , R5 ); | |
DIVS ( R3 , R5 ); | |
DIVS ( R4 , R5 ); | |
DIVS ( R6 , R5 ); | |
DIVS ( R7 , R5 ); | |
DIVS ( R5 , R5 ); | |
CHECKREG r0, 0x02460005; | |
CHECKREG r1, 0x00000001; | |
CHECKREG r2, 0x268ACF12; | |
CHECKREG r3, 0x48ACF134; | |
CHECKREG r4, 0x6ACF1356; | |
CHECKREG r5, 0x0001FFE3; | |
CHECKREG r6, 0xAF13579A; | |
CHECKREG r7, 0xD13579BC; | |
imm32 r0, 0x51230002; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0xb1256790; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x956789ab; | |
imm32 r5, 0x86789abc; | |
imm32 r6, 0x00000000; | |
imm32 r7, 0x789abcde; | |
R6.L = 24; | |
DIVS ( R0 , R6 ); | |
DIVS ( R1 , R6 ); | |
DIVS ( R2 , R6 ); | |
DIVS ( R3 , R6 ); | |
DIVS ( R4 , R6 ); | |
DIVS ( R5 , R6 ); | |
DIVS ( R7 , R6 ); | |
DIVS ( R6 , R6 ); | |
CHECKREG r0, 0xA2460004; | |
CHECKREG r1, 0x2468ACF0; | |
CHECKREG r2, 0x624ACF21; | |
CHECKREG r3, 0x68ACF134; | |
CHECKREG r4, 0x2ACF1357; | |
CHECKREG r5, 0x0CF13579; | |
CHECKREG r6, 0x00000030; | |
CHECKREG r7, 0xF13579BC; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x82345678; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0xa456789a; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0xc6789abc; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0x00000000; | |
R7.L = -24; | |
DIVS ( R0 , R7 ); | |
DIVS ( R1 , R7 ); | |
DIVS ( R2 , R7 ); | |
DIVS ( R3 , R7 ); | |
DIVS ( R4 , R7 ); | |
DIVS ( R5 , R7 ); | |
DIVS ( R6 , R7 ); | |
DIVS ( R7 , R7 ); | |
CHECKREG r0, 0x02460005; | |
CHECKREG r1, 0x0468ACF0; | |
CHECKREG r2, 0x268ACF12; | |
CHECKREG r3, 0x48ACF134; | |
CHECKREG r4, 0x6ACF1356; | |
CHECKREG r5, 0x8CF13578; | |
CHECKREG r6, 0xAF13579A; | |
CHECKREG r7, 0x0001FFD1; | |
pass |