//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp | |
// Spec Reference: alu2op logical right | |
# mach: bfin | |
.include "testutils.inc" | |
start | |
imm32 r0, 0x00000000; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0x23456789; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x856789ab; | |
imm32 r5, 0x96789abc; | |
imm32 r6, 0xa789abcd; | |
imm32 r7, 0xb89abcde; | |
R0.L = 1; | |
R1 >>= R0; | |
R2 >>= R0; | |
R3 >>= R0; | |
R4 >>= R0; | |
R5 >>= R0; | |
R6 >>= R0; | |
R7 >>= R0; | |
R4 >>= R0; | |
R0 >>= R0; | |
CHECKREG r1, 0x091A2B3C; | |
CHECKREG r2, 0x11A2B3C4; | |
CHECKREG r3, 0x1A2B3C4D; | |
CHECKREG r4, 0x2159E26A; | |
CHECKREG r5, 0x4B3C4D5E; | |
CHECKREG r6, 0x53C4D5E6; | |
CHECKREG r7, 0x5C4D5E6F; | |
CHECKREG r0, 0x00000000; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x00000000; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0xa456789a; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0xc6789abc; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0xe89abcde; | |
R1.L = -1; | |
R0 >>= R1; | |
R2 >>= R1; | |
R3 >>= R1; | |
R4 >>= R1; | |
R5 >>= R1; | |
R6 >>= R1; | |
R7 >>= R1; | |
R1 >>= R1; | |
CHECKREG r0, 0x00000000; | |
CHECKREG r1, 0x00000000; | |
CHECKREG r2, 0x00000000; | |
CHECKREG r3, 0x00000000; | |
CHECKREG r4, 0x00000000; | |
CHECKREG r5, 0x00000000; | |
CHECKREG r6, 0x00000000; | |
CHECKREG r7, 0x00000000; | |
imm32 r0, 0x51230002; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0x00000000; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x956789ab; | |
imm32 r5, 0x86789abc; | |
imm32 r6, 0x6789abcd; | |
imm32 r7, 0x789abcde; | |
R2.L = 31; | |
R0 >>= R2; | |
R1 >>= R2; | |
R3 >>= R2; | |
R4 >>= R2; | |
R5 >>= R2; | |
R6 >>= R2; | |
R7 >>= R2; | |
R2 >>= R2; | |
CHECKREG r0, 0x00000000; | |
CHECKREG r1, 0x00000000; | |
CHECKREG r2, 0x00000000; | |
CHECKREG r3, 0x00000000; | |
CHECKREG r4, 0x00000001; | |
CHECKREG r5, 0x00000001; | |
CHECKREG r6, 0x00000000; | |
CHECKREG r7, 0x00000000; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x82345678; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0x00000000; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0xc6789abc; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0xe89abcde; | |
R3.L = -31; | |
R0 >>= R3; | |
R1 >>= R3; | |
R2 >>= R3; | |
R4 >>= R3; | |
R5 >>= R3; | |
R6 >>= R3; | |
R7 >>= R3; | |
R3 >>= R3; | |
CHECKREG r0, 0x00; | |
CHECKREG r1, 0x0; | |
CHECKREG r2, 0x0; | |
CHECKREG r3, 0x0; | |
CHECKREG r4, 0x0; | |
CHECKREG r5, 0x0; | |
CHECKREG r6, 0x0; | |
CHECKREG r7, 0x0; | |
imm32 r0, 0x00000001; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0x23456789; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x00000000; | |
imm32 r5, 0x96789abc; | |
imm32 r6, 0xa789abcd; | |
imm32 r7, 0xb89abcde; | |
R4.L = 15; | |
R1 >>= R4; | |
R2 >>= R4; | |
R3 >>= R4; | |
R0 >>= R4; | |
R5 >>= R4; | |
R6 >>= R4; | |
R7 >>= R4; | |
R4 >>= R4; | |
CHECKREG r0, 0x00000000; | |
CHECKREG r1, 0x00002468; | |
CHECKREG r2, 0x0000468A; | |
CHECKREG r3, 0x000068AC; | |
CHECKREG r4, 0x00000000; | |
CHECKREG r5, 0x00012CF1; | |
CHECKREG r6, 0x00014F13; | |
CHECKREG r7, 0x00017135; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x00000000; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0xa456789a; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0x00000000; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0xe89abcde; | |
R5.L = -15; | |
R0 >>= R5; | |
R1 >>= R5; | |
R2 >>= R5; | |
R3 >>= R5; | |
R4 >>= R5; | |
R6 >>= R5; | |
R7 >>= R5; | |
R5 >>= R5; | |
CHECKREG r0, 0x000000; | |
CHECKREG r1, 0x00000000; | |
CHECKREG r2, 0x0000; | |
CHECKREG r3, 0x0000; | |
CHECKREG r4, 0x0000; | |
CHECKREG r5, 0x00000000; | |
CHECKREG r6, 0x0000; | |
CHECKREG r7, 0x0000; | |
imm32 r0, 0x51230002; | |
imm32 r1, 0x12345678; | |
imm32 r2, 0xb1256790; | |
imm32 r3, 0x3456789a; | |
imm32 r4, 0x956789ab; | |
imm32 r5, 0x86789abc; | |
imm32 r6, 0x00000000; | |
imm32 r7, 0x789abcde; | |
R6.L = 24; | |
R0 >>= R6; | |
R1 >>= R6; | |
R2 >>= R6; | |
R3 >>= R6; | |
R4 >>= R6; | |
R5 >>= R6; | |
R7 >>= R6; | |
R6 >>= R6; | |
CHECKREG r0, 0x00000051; | |
CHECKREG r1, 0x00000012; | |
CHECKREG r2, 0x000000B1; | |
CHECKREG r3, 0x00000034; | |
CHECKREG r4, 0x00000095; | |
CHECKREG r5, 0x00000086; | |
CHECKREG r6, 0x00000000; | |
CHECKREG r7, 0x00000078; | |
imm32 r0, 0x01230002; | |
imm32 r1, 0x82345678; | |
imm32 r2, 0x93456789; | |
imm32 r3, 0xa456789a; | |
imm32 r4, 0xb56789ab; | |
imm32 r5, 0xc6789abc; | |
imm32 r6, 0xd789abcd; | |
imm32 r7, 0x00000000; | |
R7.L = -24; | |
R0 >>= R7; | |
R1 >>= R7; | |
R2 >>= R7; | |
R3 >>= R7; | |
R4 >>= R7; | |
R5 >>= R7; | |
R6 >>= R7; | |
R7 >>= R7; | |
CHECKREG r0, 0x00; | |
CHECKREG r1, 0x00; | |
CHECKREG r2, 0x00; | |
CHECKREG r3, 0x00; | |
CHECKREG r4, 0x00; | |
CHECKREG r5, 0x00; | |
CHECKREG r6, 0x00; | |
CHECKREG r7, 0x00; | |
pass |