//Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp | |
// Spec Reference: compi2opd dregs += imm7 positive | |
# mach: bfin | |
.include "testutils.inc" | |
start | |
INIT_R_REGS 0; | |
R0 += 0; | |
R1 += 1; | |
R2 += 2; | |
R3 += 3; | |
R4 += 4; | |
R5 += 5; | |
R6 += 6; | |
R7 += 7; | |
CHECKREG r0, 0x00000000; | |
CHECKREG r1, 0x00000001; | |
CHECKREG r2, 0x00000002; | |
CHECKREG r3, 0x00000003; | |
CHECKREG r4, 0x00000004; | |
CHECKREG r5, 0x00000005; | |
CHECKREG r6, 0x00000006; | |
CHECKREG r7, 0x00000007; | |
R0 += 8; | |
R1 += 9; | |
R2 += 10; | |
R3 += 11; | |
R4 += 12; | |
R5 += 13; | |
R6 += 14; | |
R7 += 15; | |
CHECKREG r0, 0x00000008; | |
CHECKREG r1, 0x0000000A; | |
CHECKREG r2, 0x0000000C; | |
CHECKREG r3, 0x0000000E; | |
CHECKREG r4, 0x00000010; | |
CHECKREG r5, 0x00000012; | |
CHECKREG r6, 0x00000014; | |
CHECKREG r7, 0x00000016; | |
R0 += 16; | |
R1 += 17; | |
R2 += 18; | |
R3 += 19; | |
R4 += 20; | |
R5 += 21; | |
R6 += 22; | |
R7 += 23; | |
CHECKREG r0, 0x00000018; | |
CHECKREG r1, 0x0000001B; | |
CHECKREG r2, 0x0000001E; | |
CHECKREG r3, 0x00000021; | |
CHECKREG r4, 0x00000024; | |
CHECKREG r5, 0x00000027; | |
CHECKREG r6, 0x0000002A; | |
CHECKREG r7, 0x0000002D; | |
R0 += 24; | |
R1 += 25; | |
R2 += 26; | |
R3 += 27; | |
R4 += 28; | |
R5 += 29; | |
R6 += 30; | |
R7 += 31; | |
CHECKREG r0, 0x00000030; | |
CHECKREG r1, 0x00000034; | |
CHECKREG r2, 0x00000038; | |
CHECKREG r3, 0x0000003C; | |
CHECKREG r4, 0x00000040; | |
CHECKREG r5, 0x00000044; | |
CHECKREG r6, 0x00000048; | |
CHECKREG r7, 0x0000004C; | |
R0 += 32; | |
R1 += 33; | |
R2 += 34; | |
R3 += 35; | |
R4 += 36; | |
R5 += 37; | |
R6 += 38; | |
R7 += 39; | |
CHECKREG r0, 0x00000050; | |
CHECKREG r1, 0x00000055; | |
CHECKREG r2, 0x0000005A; | |
CHECKREG r3, 0x0000005F; | |
CHECKREG r4, 0x00000064; | |
CHECKREG r5, 0x00000069; | |
CHECKREG r6, 0x0000006E; | |
CHECKREG r7, 0x00000073; | |
R0 += 40; | |
R1 += 41; | |
R2 += 42; | |
R3 += 43; | |
R4 += 44; | |
R5 += 45; | |
R6 += 46; | |
R7 += 47; | |
CHECKREG r0, 0x00000078; | |
CHECKREG r1, 0x0000007E; | |
CHECKREG r2, 0x00000084; | |
CHECKREG r3, 0x0000008A; | |
CHECKREG r4, 0x00000090; | |
CHECKREG r5, 0x00000096; | |
CHECKREG r6, 0x0000009C; | |
CHECKREG r7, 0x000000A2; | |
R0 += 48; | |
R1 += 49; | |
R2 += 50; | |
R3 += 51; | |
R4 += 52; | |
R5 += 53; | |
R6 += 54; | |
R7 += 55; | |
CHECKREG r0, 0x000000A8; | |
CHECKREG r1, 0x000000AF; | |
CHECKREG r2, 0x000000B6; | |
CHECKREG r3, 0x000000BD; | |
CHECKREG r4, 0x000000C4; | |
CHECKREG r5, 0x000000CB; | |
CHECKREG r6, 0x000000D2; | |
CHECKREG r7, 0x000000D9; | |
R0 += 56; | |
R1 += 57; | |
R2 += 58; | |
R3 += 59; | |
R4 += 60; | |
R5 += 61; | |
R6 += 62; | |
R7 += 63; | |
CHECKREG r0, 0x000000E0; | |
CHECKREG r1, 0x000000E8; | |
CHECKREG r2, 0x000000F0; | |
CHECKREG r3, 0x000000F8; | |
CHECKREG r4, 0x00000100; | |
CHECKREG r5, 0x00000108; | |
CHECKREG r6, 0x00000110; | |
CHECKREG r7, 0x00000118; | |
pass |