//Original:/testcases/core/c_dsp32alu_rm/c_dsp32alu_rm.dsp | |
// Spec Reference: dsp32alu | |
# mach: bfin | |
.include "testutils.inc" | |
start | |
imm32 r0, 0x35678911; | |
imm32 r1, 0x2389ab1d; | |
imm32 r2, 0x34345515; | |
imm32 r3, 0x46637717; | |
imm32 r4, 0x5567391b; | |
imm32 r5, 0x6789a31d; | |
imm32 r6, 0x744455a5; | |
imm32 r7, 0x866677a7; | |
R0 = R0 - R0 (NS); | |
R1 = R0 - R1 (NS); | |
R2 = R0 - R2 (NS); | |
R3 = R0 - R3 (NS); | |
R4 = R0 - R4 (NS); | |
R5 = R0 - R5 (NS); | |
R6 = R0 - R6 (NS); | |
R7 = R0 - R7 (NS); | |
CHECKREG r0, 0x00000000; | |
CHECKREG r1, 0xDC7654E3; | |
CHECKREG r2, 0xCBCBAAEB; | |
CHECKREG r3, 0xB99C88E9; | |
CHECKREG r4, 0xAA98C6E5; | |
CHECKREG r5, 0x98765CE3; | |
CHECKREG r6, 0x8BBBAA5B; | |
CHECKREG r7, 0x79998859; | |
imm32 r0, 0xa5678911; | |
imm32 r1, 0x4a89ab1d; | |
imm32 r2, 0x54a45515; | |
imm32 r3, 0x466a7717; | |
imm32 r4, 0x5567a91b; | |
imm32 r5, 0x6789ab1d; | |
imm32 r6, 0x74445a15; | |
imm32 r7, 0x866677a7; | |
R0 = R1 - R0 (NS); | |
R1 = R1 - R1 (NS); | |
R2 = R1 - R2 (NS); | |
R3 = R1 - R3 (NS); | |
R4 = R1 - R4 (NS); | |
R5 = R1 - R5 (NS); | |
R6 = R1 - R6 (NS); | |
R7 = R1 - R7 (NS); | |
CHECKREG r0, 0xA522220C; | |
CHECKREG r1, 0x00000000; | |
CHECKREG r2, 0xAB5BAAEB; | |
CHECKREG r3, 0xB99588E9; | |
CHECKREG r4, 0xAA9856E5; | |
CHECKREG r5, 0x987654E3; | |
CHECKREG r6, 0x8BBBA5EB; | |
CHECKREG r7, 0x79998859; | |
imm32 r0, 0xda678911; | |
imm32 r1, 0x27c9ab1d; | |
imm32 r2, 0x344c5515; | |
imm32 r3, 0x4666c717; | |
imm32 r4, 0x5567891b; | |
imm32 r5, 0x6789ab1d; | |
imm32 r6, 0x744455b5; | |
imm32 r7, 0x8666777b; | |
R0 = R2 - R0 (NS); | |
R1 = R2 - R1 (NS); | |
R2 = R2 - R2 (NS); | |
R3 = R2 - R3 (NS); | |
R4 = R2 - R4 (NS); | |
R5 = R2 - R5 (NS); | |
R6 = R2 - R6 (NS); | |
R7 = R2 - R7 (NS); | |
CHECKREG r0, 0x59E4CC04; | |
CHECKREG r1, 0x0C82A9F8; | |
CHECKREG r2, 0x00000000; | |
CHECKREG r3, 0xB99938E9; | |
CHECKREG r4, 0xAA9876E5; | |
CHECKREG r5, 0x987654E3; | |
CHECKREG r6, 0x8BBBAA4B; | |
CHECKREG r7, 0x79998885; | |
imm32 r0, 0x65678911; | |
imm32 r1, 0x7289ab1d; | |
imm32 r2, 0x84345515; | |
imm32 r3, 0x96647717; | |
imm32 r4, 0x5567591b; | |
imm32 r5, 0x6789a61d; | |
imm32 r6, 0x744d5515; | |
imm32 r7, 0x8666b777; | |
R0 = R3 - R0 (NS); | |
R1 = R3 - R1 (NS); | |
R2 = R3 - R2 (NS); | |
R3 = R3 - R3 (NS); | |
R4 = R3 - R4 (NS); | |
R5 = R3 - R5 (NS); | |
R6 = R3 - R6 (NS); | |
R7 = R3 - R7 (NS); | |
CHECKREG r0, 0x30FCEE06; | |
CHECKREG r1, 0x23DACBFA; | |
CHECKREG r2, 0x12302202; | |
CHECKREG r3, 0x00000000; | |
CHECKREG r4, 0xAA98A6E5; | |
CHECKREG r5, 0x987659E3; | |
CHECKREG r6, 0x8BB2AAEB; | |
CHECKREG r7, 0x79994889; | |
imm32 r0, 0x15678911; | |
imm32 r1, 0x2789ab1d; | |
imm32 r2, 0x34445515; | |
imm32 r3, 0x46667717; | |
imm32 r4, 0x5567891b; | |
imm32 r5, 0x6789ab1d; | |
imm32 r6, 0x74445515; | |
imm32 r7, 0x86667777; | |
R0 = R4 - R0 (NS); | |
R1 = R4 - R1 (NS); | |
R2 = R4 - R2 (NS); | |
R3 = R4 - R3 (NS); | |
R4 = R4 - R4 (NS); | |
R5 = R4 - R5 (NS); | |
R6 = R4 - R6 (NS); | |
R7 = R4 - R7 (NS); | |
CHECKREG r0, 0x4000000A; | |
CHECKREG r1, 0x2DDDDDFE; | |
CHECKREG r2, 0x21233406; | |
CHECKREG r3, 0x0F011204; | |
CHECKREG r4, 0x00000000; | |
CHECKREG r5, 0x987654E3; | |
CHECKREG r6, 0x8BBBAAEB; | |
CHECKREG r7, 0x79998889; | |
imm32 r0, 0x95678911; | |
imm32 r1, 0x8789ab1d; | |
imm32 r2, 0x74445515; | |
imm32 r3, 0x36667717; | |
imm32 r4, 0x3567891b; | |
imm32 r5, 0x6e89ab1d; | |
imm32 r6, 0x74e45515; | |
imm32 r7, 0x866e7777; | |
R0 = R5 - R0 (NS); | |
R1 = R5 - R1 (NS); | |
R2 = R5 - R2 (NS); | |
R3 = R5 - R3 (NS); | |
R4 = R5 - R4 (NS); | |
R5 = R5 - R5 (NS); | |
R6 = R5 - R6 (NS); | |
R7 = R5 - R7 (NS); | |
CHECKREG r0, 0xD922220C; | |
CHECKREG r1, 0xE7000000; | |
CHECKREG r2, 0xFA455608; | |
CHECKREG r3, 0x38233406; | |
CHECKREG r4, 0x39222202; | |
CHECKREG r5, 0x00000000; | |
CHECKREG r6, 0x8B1BAAEB; | |
CHECKREG r7, 0x79918889; | |
imm32 r0, 0x5a678911; | |
imm32 r1, 0x67c9ab1d; | |
imm32 r2, 0x744d5515; | |
imm32 r3, 0x8666b717; | |
imm32 r4, 0x9567891b; | |
imm32 r5, 0x6789db1d; | |
imm32 r6, 0x74445f15; | |
imm32 r7, 0x866677f7; | |
R0 = R6 - R0 (NS); | |
R1 = R6 - R1 (NS); | |
R2 = R6 - R2 (NS); | |
R3 = R6 - R3 (NS); | |
R4 = R6 - R4 (NS); | |
R5 = R6 - R5 (NS); | |
R6 = R6 - R6 (NS); | |
R7 = R6 - R7 (NS); | |
CHECKREG r0, 0x19DCD604; | |
CHECKREG r1, 0x0C7AB3F8; | |
CHECKREG r2, 0xFFF70A00; | |
CHECKREG r3, 0xEDDDA7FE; | |
CHECKREG r4, 0xDEDCD5FA; | |
CHECKREG r5, 0x0CBA83F8; | |
CHECKREG r6, 0x00000000; | |
CHECKREG r7, 0x79998809; | |
imm32 r0, 0x25678911; | |
imm32 r1, 0x2389ab1d; | |
imm32 r2, 0x3a455515; | |
imm32 r3, 0x46d66717; | |
imm32 r4, 0x556b891b; | |
imm32 r5, 0x6789cb1d; | |
imm32 r6, 0x74445515; | |
imm32 r7, 0x86667777; | |
R0 = R7 - R0 (NS); | |
R1 = R7 - R1 (NS); | |
R2 = R7 - R2 (NS); | |
R3 = R7 - R3 (NS); | |
R4 = R7 - R4 (NS); | |
R5 = R7 - R5 (NS); | |
R6 = R7 - R6 (NS); | |
R7 = R7 - R7 (NS); | |
CHECKREG r0, 0x60FEEE66; | |
CHECKREG r1, 0x62DCCC5A; | |
CHECKREG r2, 0x4C212262; | |
CHECKREG r3, 0x3F901060; | |
CHECKREG r4, 0x30FAEE5C; | |
CHECKREG r5, 0x1EDCAC5A; | |
CHECKREG r6, 0x12222262; | |
CHECKREG r7, 0x00000000; | |
imm32 r0, 0xd5678911; | |
imm32 r1, 0x2e89ab1d; | |
imm32 r2, 0x34f45515; | |
imm32 r3, 0x466b7717; | |
imm32 r4, 0x5567c91b; | |
imm32 r5, 0x6789ab1d; | |
imm32 r6, 0x74445115; | |
imm32 r7, 0x866a7d77; | |
R3 = R1 - R4 (S); | |
R7 = R4 - R6 (S); | |
R2 = R7 - R7 (S); | |
R4 = R5 - R0 (S); | |
R5 = R3 - R1 (S); | |
R6 = R2 - R3 (S); | |
R0 = R0 - R2 (S); | |
R1 = R6 - R5 (S); | |
CHECKREG r0, 0xD5678911; | |
CHECKREG r1, 0x7C45E719; | |
CHECKREG r2, 0x00000000; | |
CHECKREG r3, 0xD921E202; | |
CHECKREG r4, 0x7FFFFFFF; | |
CHECKREG r5, 0xAA9836E5; | |
CHECKREG r6, 0x26DE1DFE; | |
CHECKREG r7, 0xE1237806; | |
imm32 r0, 0x15678911; | |
imm32 r1, 0x2789ab1d; | |
imm32 r2, 0x34445515; | |
imm32 r3, 0x46667717; | |
imm32 r4, 0x5567891b; | |
imm32 r5, 0x6789ab1d; | |
imm32 r6, 0x74445515; | |
imm32 r7, 0x86667777; | |
R3 = R3 - R3 (S); | |
R1 = R7 - R6 (S); | |
R4 = R1 - R2 (S); | |
R7 = R4 - R0 (S); | |
R5 = R6 - R4 (S); | |
R2 = R5 - R5 (S); | |
R6 = R2 - R1 (S); | |
R0 = R0 - R7 (S); | |
CHECKREG r0, 0x7FFFFFFF; | |
CHECKREG r1, 0x80000000; | |
CHECKREG r2, 0x00000000; | |
CHECKREG r3, 0x00000000; | |
CHECKREG r4, 0x80000000; | |
CHECKREG r5, 0x7FFFFFFF; | |
CHECKREG r6, 0x7FFFFFFF; | |
CHECKREG r7, 0x80000000; | |
pass |