| //Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp |
| // Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0 |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| |
| |
| |
| imm32 r0, 0x95679911; |
| imm32 r1, 0x2789ab1d; |
| imm32 r2, 0x34945515; |
| imm32 r3, 0x46967717; |
| imm32 r4, 0x5597891b; |
| imm32 r5, 0x6989ab1d; |
| imm32 r6, 0x94445515; |
| imm32 r7, 0x96667777; |
| R0 = R0 +|+ R0, R7 = R0 -|- R0; |
| R1 = R0 +|+ R1, R6 = R0 -|- R1; |
| R2 = R0 +|+ R2, R5 = R0 -|- R2; |
| R3 = R0 +|+ R3, R4 = R0 -|- R3; |
| R4 = R0 +|+ R4, R3 = R0 -|- R4; |
| R5 = R0 +|+ R5, R2 = R0 -|- R5; |
| R6 = R0 +|+ R6, R1 = R0 -|- R6; |
| R7 = R0 +|+ R7, R0 = R0 -|- R7; |
| CHECKREG r0, 0x2ACE3222; |
| CHECKREG r1, 0x2789AB1D; |
| CHECKREG r2, 0x34945515; |
| CHECKREG r3, 0x46967717; |
| CHECKREG r4, 0x0F06ED2D; |
| CHECKREG r5, 0x21080F2F; |
| CHECKREG r6, 0x2E13B927; |
| CHECKREG r7, 0x2ACE3222; |
| |
| imm32 r0, 0x11678911; |
| imm32 r1, 0xa719ab1d; |
| imm32 r2, 0x3a415515; |
| imm32 r3, 0x46a67717; |
| imm32 r4, 0x556a891b; |
| imm32 r5, 0x6789ab1d; |
| imm32 r6, 0x74445a15; |
| imm32 r7, 0x866677a7; |
| R0 = R1 +|+ R0, R7 = R1 -|- R0; |
| R1 = R1 +|+ R1, R6 = R1 -|- R1; |
| R2 = R1 +|+ R2, R5 = R1 -|- R2; |
| R3 = R1 +|+ R3, R4 = R1 -|- R3; |
| R4 = R1 +|+ R4, R3 = R1 -|- R4; |
| R5 = R1 +|+ R5, R2 = R1 -|- R5; |
| R6 = R1 +|+ R6, R1 = R1 -|- R6; |
| R7 = R1 +|+ R7, R0 = R1 -|- R7; |
| CHECKREG r0, 0xB880342E; |
| CHECKREG r1, 0x4E32563A; |
| CHECKREG r2, 0x3A415515; |
| CHECKREG r3, 0x46A67717; |
| CHECKREG r4, 0x55BE355D; |
| CHECKREG r5, 0x6223575F; |
| CHECKREG r6, 0x4E32563A; |
| CHECKREG r7, 0xE3E47846; |
| |
| imm32 r0, 0xb567891b; |
| imm32 r1, 0x2b89abbd; |
| imm32 r2, 0x34b45b15; |
| imm32 r3, 0x466bb717; |
| imm32 r4, 0x556bb91b; |
| imm32 r5, 0x67b9ab1d; |
| imm32 r6, 0x7b4455b5; |
| imm32 r7, 0xb666777b; |
| R0 = R2 +|+ R0, R7 = R2 -|- R0; |
| R1 = R2 +|+ R1, R6 = R2 -|- R1; |
| R2 = R2 +|+ R2, R5 = R2 -|- R2; |
| R3 = R2 +|+ R3, R4 = R2 -|- R3; |
| R4 = R2 +|+ R4, R3 = R2 -|- R4; |
| R5 = R2 +|+ R5, R2 = R2 -|- R5; |
| R6 = R2 +|+ R6, R1 = R2 -|- R6; |
| R7 = R2 +|+ R7, R0 = R2 -|- R7; |
| CHECKREG r0, 0xEA1BE430; |
| CHECKREG r1, 0x603D06D2; |
| CHECKREG r2, 0x6968B62A; |
| CHECKREG r3, 0x466BB717; |
| CHECKREG r4, 0x8C65B53D; |
| CHECKREG r5, 0x6968B62A; |
| CHECKREG r6, 0x72936582; |
| CHECKREG r7, 0xE8B58824; |
| |
| imm32 r0, 0xbc678c11; |
| imm32 r1, 0x27c9cb1d; |
| imm32 r2, 0x344c5515; |
| imm32 r3, 0x46c6c717; |
| imm32 r4, 0x55678c1b; |
| imm32 r5, 0x6c89abcd; |
| imm32 r6, 0x7444551c; |
| imm32 r7, 0x8c667777; |
| R0 = R3 +|+ R0, R7 = R3 -|- R0; |
| R1 = R3 +|+ R1, R6 = R3 -|- R1; |
| R2 = R3 +|+ R2, R5 = R3 -|- R2; |
| R3 = R3 +|+ R3, R4 = R3 -|- R3; |
| R4 = R3 +|+ R4, R3 = R3 -|- R4; |
| R5 = R3 +|+ R5, R2 = R3 -|- R5; |
| R6 = R3 +|+ R6, R1 = R3 -|- R6; |
| R7 = R3 +|+ R7, R0 = R3 -|- R7; |
| CHECKREG r0, 0x032D5328; |
| CHECKREG r1, 0x6E8F9234; |
| CHECKREG r2, 0x7B121C2C; |
| CHECKREG r3, 0x8D8C8E2E; |
| CHECKREG r4, 0x8D8C8E2E; |
| CHECKREG r5, 0xA0060030; |
| CHECKREG r6, 0xAC898A28; |
| CHECKREG r7, 0x17EBC934; |
| |
| imm32 r0, 0xd56789d1; |
| imm32 r1, 0x2d89abdd; |
| imm32 r2, 0x34d455d5; |
| imm32 r3, 0x4d667717; |
| imm32 r4, 0x5dd7891b; |
| imm32 r5, 0x6789ab1d; |
| imm32 r6, 0xd44d5515; |
| imm32 r7, 0xd666d777; |
| R0 = R4 +|+ R0, R7 = R4 -|- R0; |
| R1 = R4 +|+ R1, R6 = R4 -|- R1; |
| R2 = R4 +|+ R2, R5 = R4 -|- R2; |
| R3 = R4 +|+ R3, R4 = R4 -|- R3; |
| R4 = R4 +|+ R4, R3 = R4 -|- R4; |
| R5 = R4 +|+ R5, R2 = R4 -|- R5; |
| R6 = R4 +|+ R6, R1 = R4 -|- R6; |
| R7 = R4 +|+ R7, R0 = R4 -|- R7; |
| CHECKREG r0, 0x987224BE; |
| CHECKREG r1, 0xF09446CA; |
| CHECKREG r2, 0xF7DFF0C2; |
| CHECKREG r3, 0x00000000; |
| CHECKREG r4, 0x20E22408; |
| CHECKREG r5, 0x49E5574E; |
| CHECKREG r6, 0x51300146; |
| CHECKREG r7, 0xA9522352; |
| |
| imm32 r0, 0xc567a911; |
| imm32 r1, 0x278aab1d; |
| imm32 r2, 0x3c445515; |
| imm32 r3, 0x46a67717; |
| imm32 r4, 0x55c7891b; |
| imm32 r5, 0x6a8cab1d; |
| imm32 r6, 0x7444c515; |
| imm32 r7, 0xa6667c77; |
| R0 = R5 +|+ R0, R7 = R5 -|- R0; |
| R1 = R5 +|+ R1, R6 = R5 -|- R1; |
| R2 = R5 +|+ R2, R5 = R5 -|- R2; |
| R3 = R5 +|+ R3, R4 = R5 -|- R3; |
| R4 = R5 +|+ R4, R3 = R5 -|- R4; |
| R5 = R5 +|+ R5, R2 = R5 -|- R5; |
| R6 = R5 +|+ R6, R1 = R5 -|- R6; |
| R7 = R5 +|+ R7, R0 = R5 -|- R7; |
| CHECKREG r0, 0xB76BAA04; |
| CHECKREG r1, 0x198EAC10; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x46A67717; |
| CHECKREG r4, 0x15EA34F9; |
| CHECKREG r5, 0x5C90AC10; |
| CHECKREG r6, 0x9F92AC10; |
| CHECKREG r7, 0x01B5AE1C; |
| |
| imm32 r0, 0xd5678911; |
| imm32 r1, 0x2ddddd1d; |
| imm32 r2, 0x34ddd515; |
| imm32 r3, 0x46d67717; |
| imm32 r4, 0x5d6d891b; |
| imm32 r5, 0x6789db1d; |
| imm32 r6, 0x74445d15; |
| imm32 r7, 0xd66677d7; |
| R0 = R6 +|+ R0, R7 = R6 -|- R0; |
| R1 = R6 +|+ R1, R6 = R6 -|- R1; |
| R2 = R6 +|+ R2, R5 = R6 -|- R2; |
| R3 = R6 +|+ R3, R4 = R6 -|- R3; |
| R4 = R6 +|+ R4, R3 = R6 -|- R4; |
| R5 = R6 +|+ R5, R2 = R6 -|- R5; |
| R6 = R6 +|+ R6, R1 = R6 -|- R6; |
| R7 = R6 +|+ R7, R0 = R6 -|- R7; |
| CHECKREG r0, 0xEDF12BEC; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x34DDD515; |
| CHECKREG r3, 0x46D67717; |
| CHECKREG r4, 0x45F888D9; |
| CHECKREG r5, 0x57F12ADB; |
| CHECKREG r6, 0x8CCEFFF0; |
| CHECKREG r7, 0x2BABD3F4; |
| |
| imm32 r0, 0xf567a911; |
| imm32 r1, 0x2f8aab1d; |
| imm32 r2, 0x34a45515; |
| imm32 r3, 0x4a6f7717; |
| imm32 r4, 0x5567f91b; |
| imm32 r5, 0xa789af1d; |
| imm32 r6, 0x74445515; |
| imm32 r7, 0x866677f7; |
| R0 = R7 +|+ R0, R7 = R7 -|- R0; |
| R1 = R7 +|+ R1, R6 = R7 -|- R1; |
| R2 = R7 +|+ R2, R5 = R7 -|- R2; |
| R3 = R7 +|+ R3, R4 = R7 -|- R3; |
| R4 = R7 +|+ R4, R3 = R7 -|- R4; |
| R5 = R7 +|+ R5, R2 = R7 -|- R5; |
| R6 = R7 +|+ R6, R1 = R7 -|- R6; |
| R7 = R7 +|+ R7, R0 = R7 -|- R7; |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x2F8AAB1D; |
| CHECKREG r2, 0x34A45515; |
| CHECKREG r3, 0x4A6F7717; |
| CHECKREG r4, 0xD78F26B5; |
| CHECKREG r5, 0xED5A48B7; |
| CHECKREG r6, 0xF274F2AF; |
| CHECKREG r7, 0x21FE9DCC; |
| |
| imm32 r0, 0xe5678911; |
| imm32 r1, 0x2e89ab1d; |
| imm32 r2, 0x34e45515; |
| imm32 r3, 0x46667717; |
| imm32 r4, 0x556e891b; |
| imm32 r5, 0x6789ab1d; |
| imm32 r6, 0x7444e515; |
| imm32 r7, 0x86667e77; |
| R4 = R2 +|+ R5, R3 = R2 -|- R5 (S); |
| R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO); |
| R2 = R6 +|+ R2, R0 = R6 -|- R2 (SCO); |
| R3 = R4 +|+ R0, R2 = R4 -|- R0 (S); |
| R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO); |
| R6 = R1 +|+ R7, R1 = R1 -|- R7 (SCO); |
| R5 = R0 +|+ R4, R7 = R0 -|- R4 (S); |
| R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO); |
| CHECKREG r0, 0x90003F60; |
| CHECKREG r1, 0x8FFF7371; |
| CHECKREG r2, 0x7FFFC0D2; |
| CHECKREG r3, 0x0FFF3F92; |
| CHECKREG r4, 0x0BB38FFF; |
| CHECKREG r5, 0x0FFF3F92; |
| CHECKREG r6, 0x29330EA9; |
| CHECKREG r7, 0x80003F2E; |
| |
| imm32 r0, 0xd5678911; |
| imm32 r1, 0xff89ab1d; |
| imm32 r2, 0x34f45515; |
| imm32 r3, 0x46667717; |
| imm32 r4, 0x556f891b; |
| imm32 r5, 0x6789fb1d; |
| imm32 r6, 0x74445f15; |
| imm32 r7, 0x866677f7; |
| R4 = R3 +|+ R3, R5 = R3 -|- R3 (SCO); |
| R1 = R6 +|+ R1, R6 = R6 -|- R1 (SCO); |
| R6 = R1 +|+ R4, R4 = R1 -|- R4 (S); |
| R7 = R4 +|+ R2, R0 = R4 -|- R2 (S); |
| R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO); |
| R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO); |
| R5 = R7 +|+ R7, R3 = R7 -|- R7 (SCO); |
| R0 = R0 +|+ R0, R2 = R0 -|- R0 (SCO); |
| CHECKREG r0, 0x80008000; |
| CHECKREG r1, 0xD516B4F5; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x00000000; |
| CHECKREG r4, 0xF3CE8A33; |
| CHECKREG r5, 0x00000000; |
| CHECKREG r6, 0x7FFF7FFF; |
| CHECKREG r7, 0x00000000; |
| |
| |
| |
| pass |