| //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_s/c_dsp32mac_pair_a1a0_s.dsp |
| // Spec Reference: dsp32mac pair a1a0 S |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| A1 = A0 = 0; |
| |
| // The result accumulated in A , and stored to a reg half |
| imm32 r0, 0x63545abd; |
| imm32 r1, 0x86bcfec7; |
| imm32 r2, 0xa8645679; |
| imm32 r3, 0x00860007; |
| imm32 r4, 0xefb86569; |
| imm32 r5, 0x1235860b; |
| imm32 r6, 0x000c086d; |
| imm32 r7, 0x678e0086; |
| R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (S2RND); |
| P3 = A1.w; |
| P4 = A0.w; |
| R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (S2RND); |
| P5 = A1.w; |
| SP = A0.w; |
| R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (S2RND); |
| FP = A1.w; |
| CHECKREG r0, 0xFFF66AF0; |
| CHECKREG r1, 0x0009753C; |
| CHECKREG r2, 0x00675E70; |
| CHECKREG r3, 0x5E8D5630; |
| CHECKREG r4, 0x116128E0; |
| CHECKREG r5, 0xECD7B7C0; |
| CHECKREG r6, 0xFE443BAC; |
| CHECKREG r7, 0xFE443BAC; |
| CHECKREG p1, 0xFF221DD6; |
| CHECKREG p2, 0xFF221DD6; |
| CHECKREG p3, 0x0004BA9E; |
| CHECKREG p4, 0xFFFB3578; |
| CHECKREG p5, 0x2F46AB18; |
| CHECKREG sp, 0x0033AF38; |
| CHECKREG fp, 0xF66BDBE0; |
| |
| imm32 r0, 0x98764abd; |
| imm32 r1, 0xa1bcf4c7; |
| imm32 r2, 0xa1145649; |
| imm32 r3, 0x00010005; |
| imm32 r4, 0xefbc1569; |
| imm32 r5, 0x1235010b; |
| imm32 r6, 0x000c001d; |
| imm32 r7, 0x678e0001; |
| A0 = R2; |
| A1 = R3; |
| R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (S2RND); |
| P2 = A0.w; |
| P3 = A1.w; |
| P4 = A0.w; |
| R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (S2RND); |
| P5 = A1.w; |
| SP = A0.w; |
| R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (S2RND); |
| FP = A0.w; |
| CHECKREG r0, 0xFC6F3BF8; |
| CHECKREG r1, 0xFCAF6688; |
| CHECKREG r2, 0xFC404FA0; |
| CHECKREG r3, 0xFC807A30; |
| CHECKREG r4, 0xF2E4F3AC; |
| CHECKREG r5, 0x1229EEF2; |
| CHECKREG r6, 0x000C001D; |
| CHECKREG r7, 0x678E0001; |
| CHECKREG p1, 0x0914F779; |
| CHECKREG p2, 0xFFFC4AC8; |
| CHECKREG p3, 0x0000AC92; |
| CHECKREG p4, 0xFFFC4AC8; |
| CHECKREG p5, 0xFE403D18; |
| CHECKREG sp, 0xFE2027D0; |
| CHECKREG fp, 0xFE379DFC; |
| |
| imm32 r0, 0x7136459d; |
| imm32 r1, 0xabd69ec7; |
| imm32 r2, 0x71145679; |
| imm32 r3, 0x08010007; |
| imm32 r4, 0xef9c1569; |
| imm32 r5, 0x1225010b; |
| imm32 r6, 0x0003401d; |
| imm32 r7, 0x678e0561; |
| A0 = R0; |
| A1 = R1; |
| R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (S2RND); |
| P3 = A1.w; |
| P4 = A0.w; |
| R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (S2RND); |
| P5 = A1.w; |
| SP = A0.w; |
| R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (S2RND); |
| FP = A0.w; |
| CHECKREG r0, 0x7FFFFFFF; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x71145679; |
| CHECKREG r3, 0x08010007; |
| CHECKREG r4, 0x7FFFFFFF; |
| CHECKREG r5, 0x0011A900; |
| CHECKREG r6, 0x000C5E30; |
| CHECKREG r7, 0x000C5E30; |
| CHECKREG p1, 0x7E10BF43; |
| CHECKREG p2, 0xCB200616; |
| CHECKREG p3, 0x00062F18; |
| CHECKREG p5, 0x00000000; |
| CHECKREG p4, 0x00062F18; |
| CHECKREG sp, 0x69C62F18; |
| CHECKREG fp, 0x69CF0398; |
| |
| imm32 r0, 0x123489bd; |
| imm32 r1, 0x91bcfec7; |
| imm32 r2, 0xa9145679; |
| imm32 r3, 0xd0910007; |
| imm32 r4, 0xedb91569; |
| imm32 r5, 0xd235910b; |
| imm32 r6, 0x0d0c0999; |
| imm32 r7, 0x67de0009; |
| A0 = R0; |
| A1 = R1; |
| R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (S2RND); |
| P3 = A1.w; |
| P4 = A0.w; |
| R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (S2RND); |
| P5 = A1.w; |
| SP = A0.w; |
| R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (S2RND); |
| FP = A0.w; |
| CHECKREG r0, 0xFFF3DD34; |
| CHECKREG r1, 0x80000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x7FFFFFFF; |
| CHECKREG r4, 0xFFEAE6E8; |
| CHECKREG r5, 0xFFEAE6E8; |
| CHECKREG r6, 0xFACD5268; |
| CHECKREG r7, 0xFFE66AC8; |
| CHECKREG p1, 0xA2B53ED1; |
| CHECKREG p2, 0xFFF9EE9A; |
| CHECKREG p3, 0x56EC0000; |
| CHECKREG p4, 0x00000000; |
| CHECKREG p5, 0xFFF57374; |
| CHECKREG sp, 0xFFF57374; |
| CHECKREG fp, 0xFD66A934; |
| |
| imm32 r0, 0x63545abd; |
| imm32 r1, 0x86bcfec7; |
| imm32 r2, 0xa8645679; |
| imm32 r3, 0x00860007; |
| imm32 r4, 0xefb86569; |
| imm32 r5, 0x1235860b; |
| imm32 r6, 0x000c086d; |
| imm32 r7, 0x678e0086; |
| A0 = R0; |
| A1 = R1; |
| R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R1 = ( A1 -= R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (S2RND); |
| P3 = A1.w; |
| P4 = A0.w; |
| R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (S2RND); |
| P5 = A1.w; |
| SP = A0.w; |
| R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (S2RND); |
| FP = A0.w; |
| CHECKREG r0, 0xFFF66AF0; |
| CHECKREG r1, 0x80000000; |
| CHECKREG r2, 0x20866AF0; |
| CHECKREG r3, 0x80000000; |
| CHECKREG r4, 0x31803560; |
| CHECKREG r5, 0x80000000; |
| CHECKREG r6, 0xFE443BAC; |
| CHECKREG r7, 0x80000000; |
| CHECKREG p1, 0x864E0DB2; |
| CHECKREG p2, 0xFF221DD6; |
| CHECKREG p3, 0x864BB063; |
| CHECKREG p4, 0xFFFB3578; |
| CHECKREG p5, 0x864BB063; |
| CHECKREG sp, 0x10433578; |
| CHECKREG fp, 0x18C01AB0; |
| |
| imm32 r0, 0x98764abd; |
| imm32 r1, 0xa1bcf4c7; |
| imm32 r2, 0xa1145649; |
| imm32 r3, 0x00010005; |
| imm32 r4, 0xefbc1569; |
| imm32 r5, 0x1235010b; |
| imm32 r6, 0x000c001d; |
| imm32 r7, 0x678e0001; |
| A0 = R0; |
| A1 = R1; |
| R5 = A1, R4 = ( A0 = R3.L * R0.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R1 = A1, R0 = ( A0 = R2.H * R1.L ) (S2RND); |
| P3 = A1.w; |
| P4 = A0.w; |
| R3 = A1, R2 = ( A0 += R7.H * R5.H ) (S2RND); |
| P5 = A1.w; |
| SP = A0.w; |
| R1 = A1, R0 = ( A0 += R4.L * R6.H ) (S2RND); |
| FP = A1.w; |
| CHECKREG r0, 0x80000000; |
| CHECKREG r1, 0x80000000; |
| CHECKREG r2, 0x80000000; |
| CHECKREG r3, 0x80000000; |
| CHECKREG r4, 0x0005D6C4; |
| CHECKREG r5, 0x80000000; |
| CHECKREG r6, 0x000C001D; |
| CHECKREG r7, 0x678E0001; |
| CHECKREG p1, 0xA1BCF4C7; |
| CHECKREG p2, 0x0002EB62; |
| CHECKREG p3, 0xA1BCF4C7; |
| CHECKREG p4, 0x08528D18; |
| CHECKREG p5, 0xA1BCF4C7; |
| CHECKREG sp, 0xA0C48D18; |
| CHECKREG fp, 0xA1BCF4C7; |
| |
| imm32 r0, 0x7136459d; |
| imm32 r1, 0xabd69ec7; |
| imm32 r2, 0x71145679; |
| imm32 r3, 0x08010007; |
| imm32 r4, 0xef9c1569; |
| imm32 r5, 0x1225010b; |
| imm32 r6, 0x0003401d; |
| imm32 r7, 0x678e0561; |
| A0 = R0; |
| A1 = R1; |
| R5 = ( A1 += R1.H * R6.L ) (M), R4 = ( A0 = R1.L * R6.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R7 = A1, R6 = ( A0 -= R4.H * R3.L ) (S2RND); |
| P3 = A1.w; |
| P4 = A0.w; |
| R1 = ( A1 = R2.H * R5.L ) (M), R0 = ( A0 += R2.H * R5.H ) (S2RND); |
| P5 = A1.w; |
| SP = A0.w; |
| R5 = A1, R4 = ( A0 += R0.L * R7.H ) (S2RND); |
| FP = A1.w; |
| CHECKREG r0, 0x80000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x71145679; |
| CHECKREG r3, 0x08010007; |
| CHECKREG r4, 0x80000000; |
| CHECKREG r5, 0x00000000; |
| CHECKREG r6, 0x9EA59954; |
| CHECKREG r7, 0x80000000; |
| CHECKREG p1, 0x96C29605; |
| CHECKREG p2, 0xCF4D7916; |
| CHECKREG p3, 0x96C29605; |
| CHECKREG p4, 0xCF52CCAA; |
| CHECKREG p5, 0x00000000; |
| CHECKREG sp, 0x5E3ECCAA; |
| CHECKREG fp, 0x00000000; |
| |
| imm32 r0, 0x123489bd; |
| imm32 r1, 0x91bcfec7; |
| imm32 r2, 0xa9145679; |
| imm32 r3, 0xd0910007; |
| imm32 r4, 0xedb91569; |
| imm32 r5, 0xd235910b; |
| imm32 r6, 0x0d0c0999; |
| imm32 r7, 0x67de0009; |
| A0 = R0; |
| A1 = R1; |
| R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (S2RND); |
| P1 = A1.w; |
| P2 = A0.w; |
| R3 = ( A1 -= R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (S2RND); |
| P3 = A1.w; |
| P4 = A0.w; |
| R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND); |
| P5 = A0.w; |
| SP = A1.w; |
| R7 = A1, R6 = ( A0 += R4.L * R6.H ) (S2RND); |
| FP = A0.w; |
| CHECKREG r0, 0x24753646; |
| CHECKREG r1, 0x80000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x80000000; |
| CHECKREG r4, 0xC4D53E28; |
| CHECKREG r5, 0x1D9560EC; |
| CHECKREG r6, 0xD18105A8; |
| CHECKREG r7, 0x1D9560EC; |
| CHECKREG p1, 0x91BCFEC7; |
| CHECKREG p2, 0x123A9B23; |
| CHECKREG p3, 0xBD32FEC7; |
| CHECKREG p4, 0x00000000; |
| CHECKREG p5, 0xE26A9F14; |
| CHECKREG sp, 0x0ECAB076; |
| CHECKREG fp, 0xE8C082D4; |
| |
| pass |