| //Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp |
| // Spec Reference: dsp32shift fdep x |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| imm32 r0, 0x00000001; |
| imm32 r1, 0x01000801; |
| imm32 r2, 0x08200802; |
| imm32 r3, 0x08030803; |
| imm32 r4, 0x08004804; |
| imm32 r5, 0x08000505; |
| imm32 r6, 0x08000866; |
| imm32 r7, 0x08000807; |
| R1 = DEPOSIT( R1, R0 ); |
| R2 = DEPOSIT( R2, R0 ); |
| R3 = DEPOSIT( R3, R0 ); |
| R4 = DEPOSIT( R4, R0 ) (X); |
| R5 = DEPOSIT( R5, R0 ); |
| R6 = DEPOSIT( R6, R0 ); |
| R7 = DEPOSIT( R7, R0 ) (X); |
| R0 = DEPOSIT( R0, R0 ); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x01000800; |
| CHECKREG r2, 0x08200802; |
| CHECKREG r3, 0x08030802; |
| CHECKREG r4, 0x00000000; |
| CHECKREG r5, 0x08000504; |
| CHECKREG r6, 0x08000866; |
| CHECKREG r7, 0x00000000; |
| |
| imm32 r0, 0x0900d001; |
| imm32 r1, 0x09000002; |
| imm32 r2, 0x09000002; |
| imm32 r3, 0x09100003; |
| imm32 r4, 0x09020004; |
| imm32 r5, 0x09003005; |
| imm32 r6, 0x09000406; |
| imm32 r7, 0x09000057; |
| R0 = DEPOSIT( R0, R1 ); |
| R2 = DEPOSIT( R2, R1 ); |
| R3 = DEPOSIT( R3, R1 ); |
| R4 = DEPOSIT( R4, R1 ); |
| R5 = DEPOSIT( R5, R1 ) (X); |
| R6 = DEPOSIT( R6, R1 ); |
| R7 = DEPOSIT( R7, R1 ) (X); |
| R1 = DEPOSIT( R1, R1 ); |
| CHECKREG r0, 0x0900D000; |
| CHECKREG r1, 0x09000000; |
| CHECKREG r2, 0x09000000; |
| CHECKREG r3, 0x09100000; |
| CHECKREG r4, 0x09020004; |
| CHECKREG r5, 0x00000000; |
| CHECKREG r6, 0x09000404; |
| CHECKREG r7, 0x00000000; |
| |
| |
| imm32 r0, 0x0a00e001; |
| imm32 r1, 0x0a00e001; |
| imm32 r2, 0x0a00000f; |
| imm32 r3, 0x0a000010; |
| imm32 r4, 0x0a00e004; |
| imm32 r5, 0x0a00e005; |
| imm32 r6, 0x0a00e006; |
| imm32 r7, 0x0a00e007; |
| R0 = DEPOSIT( R0, R2 ); |
| R1 = DEPOSIT( R1, R2 ); |
| R3 = DEPOSIT( R3, R2 ); |
| R4 = DEPOSIT( R4, R2 ); |
| R5 = DEPOSIT( R5, R2 ); |
| R6 = DEPOSIT( R6, R2 ); |
| R7 = DEPOSIT( R7, R2 ); |
| R2 = DEPOSIT( R2, R2 ); |
| CHECKREG r0, 0x0A008A00; |
| CHECKREG r1, 0x0A008A00; |
| CHECKREG r2, 0x0A000A00; |
| CHECKREG r3, 0x0A000A00; |
| CHECKREG r4, 0x0A008A00; |
| CHECKREG r5, 0x0A008A00; |
| CHECKREG r6, 0x0A008A00; |
| CHECKREG r7, 0x0A008A00; |
| |
| imm32 r0, 0x4b00f001; |
| imm32 r1, 0x5b00f001; |
| imm32 r2, 0x6b00f002; |
| imm32 r3, 0x9f000010; |
| imm32 r4, 0x8b00f004; |
| imm32 r5, 0x0900f005; |
| imm32 r6, 0x0b00f006; |
| imm32 r7, 0x0b0af007; |
| R0 = DEPOSIT( R0, R3 ); |
| R1 = DEPOSIT( R1, R3 ); |
| R2 = DEPOSIT( R2, R3 ) (X); |
| R4 = DEPOSIT( R4, R3 ); |
| R5 = DEPOSIT( R5, R3 ); |
| R6 = DEPOSIT( R6, R3 ) (X); |
| R7 = DEPOSIT( R7, R3 ); |
| R3 = DEPOSIT( R3, R3 ); |
| CHECKREG r0, 0x4B009F00; |
| CHECKREG r1, 0x5B009F00; |
| CHECKREG r2, 0xFFFF9F00; |
| CHECKREG r3, 0x9F009F00; |
| CHECKREG r4, 0x8B009F00; |
| CHECKREG r5, 0x09009F00; |
| CHECKREG r6, 0xFFFF9F00; |
| CHECKREG r7, 0x0B0A9F00; |
| |
| imm32 r0, 0x0c0000c0; |
| imm32 r1, 0x0c0100c0; |
| imm32 r2, 0x0c0200c0; |
| imm32 r3, 0x0c0300c0; |
| imm32 r4, 0x0c04000c; |
| imm32 r5, 0x0c0500c0; |
| imm32 r6, 0x0c0600c0; |
| imm32 r7, 0x0c0700c0; |
| R0 = DEPOSIT( R0, R4 ); |
| R1 = DEPOSIT( R1, R4 ); |
| R2 = DEPOSIT( R2, R4 ); |
| R3 = DEPOSIT( R3, R4 ); |
| R5 = DEPOSIT( R5, R4 ) (X); |
| R6 = DEPOSIT( R6, R4 ); |
| R7 = DEPOSIT( R7, R4 ); |
| R4 = DEPOSIT( R4, R4 ); |
| CHECKREG r0, 0x0C000C04; |
| CHECKREG r1, 0x0C010C04; |
| CHECKREG r2, 0x0C020C04; |
| CHECKREG r3, 0x0C030C04; |
| CHECKREG r4, 0x0C040C04; |
| CHECKREG r5, 0xFFFFFC04; |
| CHECKREG r6, 0x0C060C04; |
| CHECKREG r7, 0x0C070C04; |
| |
| imm32 r0, 0xa00100d0; |
| imm32 r1, 0xa00100d1; |
| imm32 r2, 0xa00200d0; |
| imm32 r3, 0xa00300d0; |
| imm32 r4, 0xa00400d0; |
| imm32 r5, 0xa0050007; |
| imm32 r6, 0xa00600d0; |
| imm32 r7, 0xa00700d0; |
| R5 = DEPOSIT( R0, R5 ); |
| R6 = DEPOSIT( R1, R5 ) (X); |
| R7 = DEPOSIT( R2, R5 ); |
| R0 = DEPOSIT( R3, R5 ); |
| R1 = DEPOSIT( R4, R5 ) (X); |
| R2 = DEPOSIT( R6, R5 ); |
| R3 = DEPOSIT( R7, R5 ); |
| R4 = DEPOSIT( R5, R5 ); |
| CHECKREG r0, 0xA00300C1; |
| CHECKREG r1, 0x00000001; |
| CHECKREG r2, 0x00000001; |
| CHECKREG r3, 0xA00200C1; |
| CHECKREG r4, 0xA0010081; |
| CHECKREG r5, 0xA0010085; |
| CHECKREG r6, 0x00000001; |
| CHECKREG r7, 0xA00200C1; |
| |
| imm32 r0, 0xb0010000; |
| imm32 r1, 0xb0010000; |
| imm32 r2, 0xb002000f; |
| imm32 r3, 0xb0030000; |
| imm32 r4, 0xb0040000; |
| imm32 r5, 0xb0050000; |
| imm32 r6, 0x00237809; |
| imm32 r7, 0xb0070000; |
| R0 = DEPOSIT( R0, R6 ); |
| R1 = DEPOSIT( R1, R6 ); |
| R2 = DEPOSIT( R2, R6 ); |
| R3 = DEPOSIT( R3, R6 ) (X); |
| R4 = DEPOSIT( R4, R6 ); |
| R5 = DEPOSIT( R5, R6 ); |
| R6 = DEPOSIT( R6, R6 ); |
| R7 = DEPOSIT( R7, R6 ); |
| CHECKREG r0, 0x23010000; |
| CHECKREG r1, 0x23010000; |
| CHECKREG r2, 0x2302000F; |
| CHECKREG r3, 0x23030000; |
| CHECKREG r4, 0x23040000; |
| CHECKREG r5, 0x23050000; |
| CHECKREG r6, 0x23237809; |
| CHECKREG r7, 0x23070000; |
| |
| imm32 r0, 0xd00100e0; |
| imm32 r1, 0xd00100e0; |
| imm32 r2, 0xd00200e0; |
| imm32 r3, 0xd00300e0; |
| imm32 r4, 0xd00400e0; |
| imm32 r5, 0xd00500e0; |
| imm32 r6, 0xd00600e0; |
| imm32 r7, 0x00012345; |
| R1 = DEPOSIT( R0, R7 ); |
| R2 = DEPOSIT( R1, R7 ); |
| R3 = DEPOSIT( R2, R7 ); |
| R4 = DEPOSIT( R3, R7 ); |
| R5 = DEPOSIT( R4, R7 ) (X); |
| R6 = DEPOSIT( R5, R7 ); |
| R7 = DEPOSIT( R6, R7 ) (X); |
| R0 = DEPOSIT( R7, R7 ); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0xD0010008; |
| CHECKREG r2, 0xD0010008; |
| CHECKREG r3, 0xD0010008; |
| CHECKREG r4, 0xD0010008; |
| CHECKREG r5, 0x00000008; |
| CHECKREG r6, 0x00000008; |
| CHECKREG r7, 0x00000008; |
| |
| |
| pass |